From: lkcl Date: Sun, 24 Jan 2021 13:37:42 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~354 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78e0bc69fee051f3158431daa252b5d8ea4a0d49;p=libreriscv.git --- diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 3fcb519eb..7317a37ea 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -13,7 +13,7 @@ Links: Vectorisation of Load and Store requires creation, from scalar operations, a number of different modes: -* fixed stride (contiguous sequence with no gaps) +* fixed stride (contiguous sequence with no gaps) aka "unit" stride * element strided (sequential but regularly offset, with gaps) * vector indexed (vector of base addresses and vector of offsets) * fail-first on the same (where it makes sense to do so) @@ -284,7 +284,7 @@ LD/ST, will give that same capability, with far more flexibility. this section covers assembly notation for the immediate and indexed LD/ST. the summary is that in immediate mode for LD it is not clear that if the destination register is Vectorised `RT.v` but the source `imm(RA)` is scalar -the memory being read is *still a vector load*. +the memory being read is *still a vector load*, known as "unit or element strides". This anomaly is made clear with the following notation: