From: H.J. Lu Date: Tue, 1 Apr 2008 19:12:31 +0000 (-0700) Subject: i386.md (smaxmin): New. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=78e8956be7341fa4e60420e762b4c8e24cf58eef;p=gcc.git i386.md (smaxmin): New. 2008-04-01 H.J. Lu * config/i386/i386.md (smaxmin): New. (umaxmin): Likewise. (maxminiprefix): Likewise. (maxminfprefix): Likewise. (3): Likewise. (smin3): Removed. (smax3): Likewise. * config/i386/mmx.md (mmx_v2sf3): New. (mmx_v4hi3): Likewise. (mmx_v8qi3): Likewise. (mmx_smaxv2sf3): Removed. (mmx_sminv2sf3): Likewise. (mmx_umaxv8qi3): Likewise. (mmx_smaxv4hi3): Likewise. (mmx_uminv8qi3): Likewise. (mmx_sminv4hi3): Likewise. * config/i386/sse.md (3): New. (*3): Likewise. (_vm3): Likewise. (3): Likewise. (*3_finite): Likewise. (*3): Likewise. (_vm3): Likewise. (sse3_hv4sf3): Likewise. (sse3_hv2df3): Likewise. (v16qi3): Likewise. (*v16qi3): Likewise. (v8hi3): Likewise. (*v8hi3): Likewise. (*sse4_1_3): Likewise. (*sse4_1_3): Likewise. (add3): Removed. (*add3): Likewise. (_vmadd3): Likewise. (sub3): Likewise. (*sub3): Likewise. (_vmsub3): Likewise. (smin3): Likewise. (*smin3_finite): Likewise. (*smin3): Likewise. (_vmsmin3): Likewise. (smax3): Likewise. (*smax3_finite): Likewise. (*smax3): Likewise. (_vmsmax3): Likewise. (sse3_haddv4sf3): Likewise. (sse3_haddv2df3): Likewise. (sse3_hsubv4sf3): Likewise. (sse3_hsubv2df3): Likewise. (umaxv16qi3): Likewise. (*umaxv16qi3): Likewise. (smaxv8hi3): Likewise. (*smaxv8hi3): Likewise. (*sse4_1_smax3): Likewise. (*sse4_1_umax3): Likewise. (uminv16qi3): Likewise. (*uminv16qi3): Likewise. (sminv8hi3): Likewise. (*sminv8hi3): Likewise. (*sse4_1_smin3): Likewise. (*sse4_1_umin3): Likewise. From-SVN: r133797 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 358a8eff6cc..a2118e95083 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,7 +1,73 @@ +2008-04-01 H.J. Lu + + * config/i386/i386.md (smaxmin): New. + (umaxmin): Likewise. + (maxminiprefix): Likewise. + (maxminfprefix): Likewise. + (3): Likewise. + (smin3): Removed. + (smax3): Likewise. + + * config/i386/mmx.md (mmx_v2sf3): New. + (mmx_v4hi3): Likewise. + (mmx_v8qi3): Likewise. + (mmx_smaxv2sf3): Removed. + (mmx_sminv2sf3): Likewise. + (mmx_umaxv8qi3): Likewise. + (mmx_smaxv4hi3): Likewise. + (mmx_uminv8qi3): Likewise. + (mmx_sminv4hi3): Likewise. + + * config/i386/sse.md (3): New. + (*3): Likewise. + (_vm3): Likewise. + (3): Likewise. + (*3_finite): Likewise. + (*3): Likewise. + (_vm3): Likewise. + (sse3_hv4sf3): Likewise. + (sse3_hv2df3): Likewise. + (v16qi3): Likewise. + (*v16qi3): Likewise. + (v8hi3): Likewise. + (*v8hi3): Likewise. + (*sse4_1_3): Likewise. + (*sse4_1_3): Likewise. + (add3): Removed. + (*add3): Likewise. + (_vmadd3): Likewise. + (sub3): Likewise. + (*sub3): Likewise. + (_vmsub3): Likewise. + (smin3): Likewise. + (*smin3_finite): Likewise. + (*smin3): Likewise. + (_vmsmin3): Likewise. + (smax3): Likewise. + (*smax3_finite): Likewise. + (*smax3): Likewise. + (_vmsmax3): Likewise. + (sse3_haddv4sf3): Likewise. + (sse3_haddv2df3): Likewise. + (sse3_hsubv4sf3): Likewise. + (sse3_hsubv2df3): Likewise. + (umaxv16qi3): Likewise. + (*umaxv16qi3): Likewise. + (smaxv8hi3): Likewise. + (*smaxv8hi3): Likewise. + (*sse4_1_smax3): Likewise. + (*sse4_1_umax3): Likewise. + (uminv16qi3): Likewise. + (*uminv16qi3): Likewise. + (sminv8hi3): Likewise. + (*sminv8hi3): Likewise. + (*sse4_1_smin3): Likewise. + (*sse4_1_umin3): Likewise. + 2008-04-01 Rafael Espindola * tree-cfg.c (verify_expr): remove in_phi. - (verify_stmt): Don't call walk_tree with verify_expr. Use + (verify_stmt): Don't call walk_tree with verify_expr. Use is_gimple_min_invariant instead of is_gimple_val. 2008-04-01 Joseph Myers diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1135799b65e..8ccb0b2b919 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -530,6 +530,16 @@ ;; Mark commutative operators as such in constraints. (define_code_attr comm [(plus "%") (minus "")]) +;; Mapping of signed max and min +(define_code_iterator smaxmin [smax smin]) + +;; Mapping of unsigned max and min +(define_code_iterator umaxmin [umax umin]) + +;; Base name for integer and FP insn mnemonic +(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")]) +(define_code_attr maxminfprefix [(smax "max") (smin "min")]) + ;; All single word integer modes. (define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")]) @@ -19505,23 +19515,13 @@ ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator ;; are undefined in this condition, we're certain this is correct. -(define_insn "smin3" - [(set (match_operand:MODEF 0 "register_operand" "=x") - (smin:MODEF - (match_operand:MODEF 1 "nonimmediate_operand" "%0") - (match_operand:MODEF 2 "nonimmediate_operand" "xm")))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" - "mins\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "mode" "")]) - -(define_insn "smax3" +(define_insn "3" [(set (match_operand:MODEF 0 "register_operand" "=x") - (smax:MODEF + (smaxmin:MODEF (match_operand:MODEF 1 "nonimmediate_operand" "%0") (match_operand:MODEF 2 "nonimmediate_operand" "xm")))] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" - "maxs\t{%2, %0|%0, %2}" + "s\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index a146231e992..63e9025b4e3 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -248,21 +248,13 @@ [(set_attr "type" "mmxmul") (set_attr "mode" "V2SF")]) -(define_insn "mmx_smaxv2sf3" +(define_insn "mmx_v2sf3" [(set (match_operand:V2SF 0 "register_operand" "=y") - (smax:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") - (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] + (smaxmin:V2SF + (match_operand:V2SF 1 "nonimmediate_operand" "%0") + (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW && ix86_binary_operator_ok (SMAX, V2SFmode, operands)" - "pfmax\\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "V2SF")]) - -(define_insn "mmx_sminv2sf3" - [(set (match_operand:V2SF 0 "register_operand" "=y") - (smin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") - (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] - "TARGET_3DNOW && ix86_binary_operator_ok (SMIN, V2SFmode, operands)" - "pfmin\\t{%2, %0|%0, %2}" + "pf\\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "V2SF")]) @@ -715,43 +707,25 @@ [(set_attr "type" "mmxmul") (set_attr "mode" "DI")]) -(define_insn "mmx_umaxv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (umax:V8QI (match_operand:V8QI 1 "nonimmediate_operand" "%0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] - "(TARGET_SSE || TARGET_3DNOW_A) - && ix86_binary_operator_ok (UMAX, V8QImode, operands)" - "pmaxub\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) - -(define_insn "mmx_smaxv4hi3" +(define_insn "mmx_v4hi3" [(set (match_operand:V4HI 0 "register_operand" "=y") - (smax:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] + (smaxmin:V4HI + (match_operand:V4HI 1 "nonimmediate_operand" "%0") + (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] "(TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (SMAX, V4HImode, operands)" - "pmaxsw\t{%2, %0|%0, %2}" + "pw\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) -(define_insn "mmx_uminv8qi3" +(define_insn "mmx_v8qi3" [(set (match_operand:V8QI 0 "register_operand" "=y") - (umin:V8QI (match_operand:V8QI 1 "nonimmediate_operand" "%0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] + (umaxmin:V8QI + (match_operand:V8QI 1 "nonimmediate_operand" "%0") + (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] "(TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (UMIN, V8QImode, operands)" - "pminub\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) - -(define_insn "mmx_sminv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (smin:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] - "(TARGET_SSE || TARGET_3DNOW_A) - && ix86_binary_operator_ok (SMIN, V4HImode, operands)" - "pminsw\t{%2, %0|%0, %2}" + "pb\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ad17209e542..e1f316b216d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -358,67 +358,36 @@ "SSE_VEC_FLOAT_MODE_P (mode)" "ix86_expand_fp_absneg_operator (ABS, mode, operands); DONE;") -(define_expand "add3" +(define_expand "3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (plus:SSEMODEF2P + (plusminus:SSEMODEF2P (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] "SSE_VEC_FLOAT_MODE_P (mode)" - "ix86_fixup_binary_operands_no_copy (PLUS, mode, operands);") + "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*add3" +(define_insn "*3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (plus:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") + (plusminus:SSEMODEF2P + (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode) - && ix86_binary_operator_ok (PLUS, mode, operands)" - "addp\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) -(define_insn "_vmadd3" +(define_insn "_vm3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (vec_merge:SSEMODEF2P - (plus:SSEMODEF2P + (plusminus:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) (match_dup 1) (const_int 1)))] "SSE_VEC_FLOAT_MODE_P (mode) - && ix86_binary_operator_ok (PLUS, V4SFmode, operands)" - "adds\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "mode" "")]) - -(define_expand "sub3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (minus:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "register_operand" "") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "ix86_fixup_binary_operands_no_copy (MINUS, mode, operands);") - -(define_insn "*sub3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (minus:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "register_operand" "0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "subp\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "mode" "")]) - -(define_insn "_vmsub3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (vec_merge:SSEMODEF2P - (minus:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "register_operand" "0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) - (match_dup 1) - (const_int 1)))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "subs\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (, V4SFmode, operands)" + "s\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) @@ -601,98 +570,52 @@ ;; isn't really correct, as those rtl operators aren't defined when ;; applied to NaNs. Hopefully the optimizers won't get too smart on us. -(define_expand "smin3" +(define_expand "3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (smin:SSEMODEF2P + (smaxmin:SSEMODEF2P (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] "SSE_VEC_FLOAT_MODE_P (mode)" { if (!flag_finite_math_only) operands[1] = force_reg (mode, operands[1]); - ix86_fixup_binary_operands_no_copy (SMIN, mode, operands); + ix86_fixup_binary_operands_no_copy (, mode, operands); }) -(define_insn "*smin3_finite" +(define_insn "*3_finite" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (smin:SSEMODEF2P + (smaxmin:SSEMODEF2P (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode) && flag_finite_math_only - && ix86_binary_operator_ok (SMIN, mode, operands)" - "minp\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) -(define_insn "*smin3" +(define_insn "*3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (smin:SSEMODEF2P + (smaxmin:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode)" - "minp\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) -(define_insn "_vmsmin3" +(define_insn "_vm3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (vec_merge:SSEMODEF2P - (smin:SSEMODEF2P + (smaxmin:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) (match_dup 1) (const_int 1)))] "SSE_VEC_FLOAT_MODE_P (mode)" - "mins\t{%2, %0|%0, %2}" + "s\t{%2, %0|%0, %2}" [(set_attr "type" "sse") (set_attr "mode" "")]) -(define_expand "smax3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (smax:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] - "SSE_VEC_FLOAT_MODE_P (mode)" -{ - if (!flag_finite_math_only) - operands[1] = force_reg (mode, operands[1]); - ix86_fixup_binary_operands_no_copy (SMAX, mode, operands); -}) - -(define_insn "*smax3_finite" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (smax:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] - "SSE_VEC_FLOAT_MODE_P (mode) && flag_finite_math_only - && ix86_binary_operator_ok (SMAX, mode, operands)" - "maxp\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "mode" "")]) - -(define_insn "*smax3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (smax:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "register_operand" "0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "maxp\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "mode" "")]) - -(define_insn "_vmsmax3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (vec_merge:SSEMODEF2P - (smax:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "register_operand" "0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")) - (match_dup 1) - (const_int 1)))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "maxs\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "mode" "")]) - ;; These versions of the min/max patterns implement exactly the operations ;; min = (op1 < op2 ? op1 : op2) ;; max = (!(op1 < op2) ? op1 : op2) @@ -748,93 +671,48 @@ [(set_attr "type" "sseadd") (set_attr "mode" "V2DF")]) -(define_insn "sse3_haddv4sf3" - [(set (match_operand:V4SF 0 "register_operand" "=x") - (vec_concat:V4SF - (vec_concat:V2SF - (plus:SF - (vec_select:SF - (match_operand:V4SF 1 "register_operand" "0") - (parallel [(const_int 0)])) - (vec_select:SF (match_dup 1) (parallel [(const_int 1)]))) - (plus:SF - (vec_select:SF (match_dup 1) (parallel [(const_int 2)])) - (vec_select:SF (match_dup 1) (parallel [(const_int 3)])))) - (vec_concat:V2SF - (plus:SF - (vec_select:SF - (match_operand:V4SF 2 "nonimmediate_operand" "xm") - (parallel [(const_int 0)])) - (vec_select:SF (match_dup 2) (parallel [(const_int 1)]))) - (plus:SF - (vec_select:SF (match_dup 2) (parallel [(const_int 2)])) - (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))] - "TARGET_SSE3" - "haddps\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "prefix_rep" "1") - (set_attr "mode" "V4SF")]) - -(define_insn "sse3_haddv2df3" - [(set (match_operand:V2DF 0 "register_operand" "=x") - (vec_concat:V2DF - (plus:DF - (vec_select:DF - (match_operand:V2DF 1 "register_operand" "0") - (parallel [(const_int 0)])) - (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) - (plus:DF - (vec_select:DF - (match_operand:V2DF 2 "nonimmediate_operand" "xm") - (parallel [(const_int 0)])) - (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] - "TARGET_SSE3" - "haddpd\t{%2, %0|%0, %2}" - [(set_attr "type" "sseadd") - (set_attr "mode" "V2DF")]) - -(define_insn "sse3_hsubv4sf3" +(define_insn "sse3_hv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=x") (vec_concat:V4SF (vec_concat:V2SF - (minus:SF + (plusminus:SF (vec_select:SF (match_operand:V4SF 1 "register_operand" "0") (parallel [(const_int 0)])) (vec_select:SF (match_dup 1) (parallel [(const_int 1)]))) - (minus:SF + (plusminus:SF (vec_select:SF (match_dup 1) (parallel [(const_int 2)])) (vec_select:SF (match_dup 1) (parallel [(const_int 3)])))) (vec_concat:V2SF - (minus:SF + (plusminus:SF (vec_select:SF (match_operand:V4SF 2 "nonimmediate_operand" "xm") (parallel [(const_int 0)])) (vec_select:SF (match_dup 2) (parallel [(const_int 1)]))) - (minus:SF + (plusminus:SF (vec_select:SF (match_dup 2) (parallel [(const_int 2)])) (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))] "TARGET_SSE3" - "hsubps\t{%2, %0|%0, %2}" + "hps\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "prefix_rep" "1") (set_attr "mode" "V4SF")]) -(define_insn "sse3_hsubv2df3" +(define_insn "sse3_hv2df3" [(set (match_operand:V2DF 0 "register_operand" "=x") (vec_concat:V2DF - (minus:DF + (plusminus:DF (vec_select:DF (match_operand:V2DF 1 "register_operand" "0") (parallel [(const_int 0)])) (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) - (minus:DF + (plusminus:DF (vec_select:DF (match_operand:V2DF 2 "nonimmediate_operand" "xm") (parallel [(const_int 0)])) (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_SSE3" - "hsubpd\t{%2, %0|%0, %2}" + "hpd\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V2DF")]) @@ -3660,36 +3538,40 @@ operands[1] = gen_lowpart (TImode, operands[1]); }) -(define_expand "umaxv16qi3" +(define_expand "v16qi3" [(set (match_operand:V16QI 0 "register_operand" "") - (umax:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "") - (match_operand:V16QI 2 "nonimmediate_operand" "")))] + (umaxmin:V16QI + (match_operand:V16QI 1 "nonimmediate_operand" "") + (match_operand:V16QI 2 "nonimmediate_operand" "")))] "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (UMAX, V16QImode, operands);") + "ix86_fixup_binary_operands_no_copy (, V16QImode, operands);") -(define_insn "*umaxv16qi3" +(define_insn "*v16qi3" [(set (match_operand:V16QI 0 "register_operand" "=x") - (umax:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "%0") - (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (UMAX, V16QImode, operands)" - "pmaxub\t{%2, %0|%0, %2}" + (umaxmin:V16QI + (match_operand:V16QI 1 "nonimmediate_operand" "%0") + (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] + "TARGET_SSE2 && ix86_binary_operator_ok (, V16QImode, operands)" + "pb\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) -(define_expand "smaxv8hi3" +(define_expand "v8hi3" [(set (match_operand:V8HI 0 "register_operand" "") - (smax:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "") - (match_operand:V8HI 2 "nonimmediate_operand" "")))] + (smaxmin:V8HI + (match_operand:V8HI 1 "nonimmediate_operand" "") + (match_operand:V8HI 2 "nonimmediate_operand" "")))] "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (SMAX, V8HImode, operands);") + "ix86_fixup_binary_operands_no_copy (, V8HImode, operands);") -(define_insn "*smaxv8hi3" +(define_insn "*v8hi3" [(set (match_operand:V8HI 0 "register_operand" "=x") - (smax:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0") - (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (SMAX, V8HImode, operands)" - "pmaxsw\t{%2, %0|%0, %2}" + (smaxmin:V8HI + (match_operand:V8HI 1 "nonimmediate_operand" "%0") + (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] + "TARGET_SSE2 && ix86_binary_operator_ok (, V8HImode, operands)" + "pw\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -3738,13 +3620,13 @@ } }) -(define_insn "*sse4_1_smax3" +(define_insn "*sse4_1_3" [(set (match_operand:SSEMODE14 0 "register_operand" "=x") - (smax:SSEMODE14 + (smaxmin:SSEMODE14 (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (SMAX, mode, operands)" - "pmaxs\t{%2, %0|%0, %2}" + "TARGET_SSE4_1 && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) @@ -3774,51 +3656,17 @@ } }) -(define_insn "*sse4_1_umax3" +(define_insn "*sse4_1_3" [(set (match_operand:SSEMODE24 0 "register_operand" "=x") - (umax:SSEMODE24 + (umaxmin:SSEMODE24 (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (UMAX, mode, operands)" - "pmaxu\t{%2, %0|%0, %2}" + "TARGET_SSE4_1 && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) -(define_expand "uminv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "") - (umin:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "") - (match_operand:V16QI 2 "nonimmediate_operand" "")))] - "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (UMIN, V16QImode, operands);") - -(define_insn "*uminv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "=x") - (umin:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "%0") - (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (UMIN, V16QImode, operands)" - "pminub\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_expand "sminv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "") - (smin:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "") - (match_operand:V8HI 2 "nonimmediate_operand" "")))] - "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (SMIN, V8HImode, operands);") - -(define_insn "*sminv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "=x") - (smin:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0") - (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (SMIN, V8HImode, operands)" - "pminsw\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - (define_expand "smin3" [(set (match_operand:SSEMODE14 0 "register_operand" "") (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "") @@ -3844,17 +3692,6 @@ } }) -(define_insn "*sse4_1_smin3" - [(set (match_operand:SSEMODE14 0 "register_operand" "=x") - (smin:SSEMODE14 - (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (SMIN, mode, operands)" - "pmins\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1") - (set_attr "mode" "TI")]) - (define_expand "umin3" [(set (match_operand:SSEMODE24 0 "register_operand" "") (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "") @@ -3880,17 +3717,6 @@ } }) -(define_insn "*sse4_1_umin3" - [(set (match_operand:SSEMODE24 0 "register_operand" "=x") - (umin:SSEMODE24 - (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (UMIN, mode, operands)" - "pminu\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1") - (set_attr "mode" "TI")]) - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral comparisons