From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 7 Apr 2022 10:56:48 +0000 (+0100)
Subject: code-comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7903468828570161671ebfcb82c489d2f2e0644e;p=nmigen-gf.git

code-comments
---

diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py
index 43257e7..07e6e34 100644
--- a/src/nmigen_gf/hdl/cldivrem.py
+++ b/src/nmigen_gf/hdl/cldivrem.py
@@ -96,10 +96,12 @@ class EqualLeadingZeroCount(Elaboratable):
         # OR-in both_ones
         m.d.comb += addend2.eq(~different)
 
+        # now [ab]use add: the last bit [carry-out] is the result
         csum = Signal(self.width + 1)
         carry_in = 1  # both have no leading zeros so far, so set carry
         m.d.comb += csum.eq(addend1 + addend2 + carry_in)
         m.d.comb += self.out.eq(csum[self.width])  # out is carry-out
+
         return m
 
 # TODO: add CLDivRem