From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 15:03:12 +0000 (+0100)
Subject: add msr to ISA in test_core.py
X-Git-Tag: div_pipeline~495
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=790c8ad018b2048008d216666a33522682df0afb;p=soc.git

add msr to ISA in test_core.py
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 17742940..cd8ca928 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -77,7 +77,8 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem)
+                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
+                          test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))