From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Mar 2021 00:31:32 +0000 (+0000)
Subject: remove blackbox attribute on SPBlock_512W64B8W
X-Git-Tag: convert-csv-opcode-to-binary~104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7912f688788e57ce52eb0357f5b33b19dc11e60c;p=soc.git

remove blackbox attribute on SPBlock_512W64B8W
---

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index e8613e55..02c4760c 100644
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -47,7 +47,8 @@ class SPBlock512W64B8W(Elaboratable):
         sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d,
                                              i_we=we, i_clk=ClockSignal())
         m.submodules += sram
-        sram.attrs['blackbox'] = 1
+        # has to be added to the actual module rather than the instance
+        # sram.attrs['blackbox'] = 1
 
         with m.If(self.enable): # in case of layout problems
             # wishbone is active if cyc and stb set