From: Eric Anholt Date: Tue, 8 Oct 2013 07:20:04 +0000 (-0700) Subject: i965: Don't forget the cube map padding on gen5+. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=791550aa8e70dd5e0bdd5a996ef66b5964cf9095;p=mesa.git i965: Don't forget the cube map padding on gen5+. We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd experimentally found to be necessary!), but while the spec still requires it on gen5, we'd been missing it in the array-layout cubemaps. Cc: "9.1 9.2" Reviewed-by: Ian Romanick Reviewed-by: Chad Versace Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index e4e66b4219c..e9128a38244 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -196,6 +196,18 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt) } } +static void +align_cube(struct intel_mipmap_tree *mt) +{ + /* The 965's sampler lays cachelines out according to how accesses + * in the texture surfaces run, so they may be "vertical" through + * memory. As a result, the docs say in Surface Padding Requirements: + * Sampling Engine Surfaces that two extra rows of padding are required. + */ + if (mt->target == GL_TEXTURE_CUBE_MAP) + mt->total_height += 2; +} + static void brw_miptree_layout_texture_array(struct brw_context *brw, struct intel_mipmap_tree *mt) @@ -220,6 +232,8 @@ brw_miptree_layout_texture_array(struct brw_context *brw, } } mt->total_height = qpitch * mt->physical_depth0; + + align_cube(mt); } static void @@ -291,13 +305,7 @@ brw_miptree_layout_texture_3d(struct brw_context *brw, } } - /* The 965's sampler lays cachelines out according to how accesses - * in the texture surfaces run, so they may be "vertical" through - * memory. As a result, the docs say in Surface Padding Requirements: - * Sampling Engine Surfaces that two extra rows of padding are required. - */ - if (mt->target == GL_TEXTURE_CUBE_MAP) - mt->total_height += 2; + align_cube(mt); } void