From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 14 Sep 2020 12:34:15 +0000 (+0100)
Subject: TLB PLRUs are of TLB_WAY_BITS width
X-Git-Tag: semi_working_ecp5~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=791602c27729a3f6c20115ee35b55253d43a1224;p=soc.git

TLB PLRUs are of TLB_WAY_BITS width
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 114aa0d2..25325c5b 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -654,7 +654,7 @@ class DCache(Elaboratable):
             return
         for i in range(TLB_SET_SIZE):
             # TLB PLRU interface
-            tlb_plru        = PLRU(WAY_BITS)
+            tlb_plru        = PLRU(TLB_WAY_BITS)
             setattr(m.submodules, "maybe_plru_%d" % i, tlb_plru)
             tlb_plru_acc_en = Signal()