From: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Fri, 29 Oct 2021 18:36:52 +0000 (+0200)
Subject: sim.blackboxes.serial: add missing Verilog blackbox.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7919993860650b2d0ad94d3f59f76a92f8598f27;p=lambdasoc.git

sim.blackboxes.serial: add missing Verilog blackbox.
---

diff --git a/lambdasoc/sim/blackboxes/serial/blackbox.v b/lambdasoc/sim/blackboxes/serial/blackbox.v
new file mode 100644
index 0000000..b4df604
--- /dev/null
+++ b/lambdasoc/sim/blackboxes/serial/blackbox.v
@@ -0,0 +1,26 @@
+(* cxxrtl_blackbox, cxxrtl_template = "DATA_BITS" *)
+module serial_rx(...);
+	parameter ID = "";
+	parameter DATA_BITS = 8;
+
+	(* cxxrtl_edge = "p" *) input clk;
+	input rst;
+	(* cxxrtl_sync, cxxrtl_width = "DATA_BITS" *) output [DATA_BITS - 1:0] data;
+	(* cxxrtl_sync *) output err_overflow;
+	(* cxxrtl_sync *) output err_frame;
+	(* cxxrtl_sync *) output err_parity;
+	(* cxxrtl_sync *) output rdy;
+	input ack;
+endmodule
+
+(* cxxrtl_blackbox, cxxrtl_template = "DATA_BITS" *)
+module serial_tx(...);
+	parameter ID = "";
+	parameter DATA_BITS = 8;
+
+	(* cxxrtl_edge = "p" *) input clk;
+	input rst;
+	(* cxxrtl_width = "DATA_BITS" *) input [DATA_BITS - 1:0] data;
+	(* cxxrtl_sync *) output rdy;
+	input ack;
+endmodule