From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 4 Mar 2022 12:37:59 +0000 (+0100)
Subject: RISC-V: make .insn actually work for 64-bit insns
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7919e5667cf6607a3d7e28b1fa7f15f3c49a4e55;p=binutils-gdb.git

RISC-V: make .insn actually work for 64-bit insns

Presently in this case, due to an undefined behavior shift, at least
with x86 cross builds I'm observing:

Error: value conflicts with instruction length `8,0x0000003f'

Eliminate the UB and extend the respective testcase.
---

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 322e0f070ba..9cc0abfda88 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3248,7 +3248,7 @@ riscv_ip_hardcode (char *str,
   insn->match = values[num - 1];
   create_insn (ip, insn);
   unsigned int bytes = riscv_insn_length (insn->match);
-  if (values[num - 1] >> (8 * bytes) != 0
+  if ((bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0)
       || (num == 2 && values[0] != bytes))
     return _("value conflicts with instruction length");
 
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index e55030ea460..b5780f42861 100644
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -71,5 +71,9 @@ Disassembly of section .text:
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+0001[ 	]+nop
 [^:]+:[ 	]+00000013[ 	]+nop
+[^:]+:[ 	]+001f 0000 0000[ 	].*
+[^:]+:[ 	]+0000003f 00000000[ 	].*
 [^:]+:[ 	]+0001[ 	]+nop
 [^:]+:[ 	]+00000013[ 	]+nop
+[^:]+:[ 	]+001f 0000 0000[ 	].*
+[^:]+:[ 	]+0000003f 00000000[ 	].*
diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
index e47f529040d..ec41acb30bd 100644
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -56,5 +56,9 @@ target:
 
 	.insn 0x0001
 	.insn 0x00000013
+	.insn 0x0000001f
+	.insn 0x0000003f
 	.insn 0x2, 0x0001
 	.insn 0x4, 0x00000013
+	.insn 6, 0x0000001f
+	.insn 8, 0x0000003f