From: Cesar Strauss <cestrauss@gmail.com>
Date: Tue, 9 Mar 2021 11:00:04 +0000 (-0300)
Subject: Enable VL==0 vector instruction skip test case
X-Git-Tag: convert-csv-opcode-to-binary~79
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79308843201af84337f83e70f907dd7717bccf37;p=soc.git

Enable VL==0 vector instruction skip test case
---

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 92e8522a..3c90e71d 100644
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -100,8 +100,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
 
-    @skip_case("VL hardware loop is not yet implemented")
-    def case_4_sv_check_vl_0(self):
+    def case_5_sv_check_vl_0(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
         isa = SVP64Asm([