From: Rafael Antognolli <rafael.antognolli@intel.com>
Date: Tue, 5 Nov 2019 23:34:53 +0000 (-0800)
Subject: intel/isl: Update mocs for DG1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=793b40924161130bedb1a4ff746a8790004304d8;p=mesa.git

intel/isl: Update mocs for DG1

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
---

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f7689d5b867..e9731616bb1 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -99,11 +99,20 @@ static void
 isl_device_setup_mocs(struct isl_device *dev)
 {
    if (dev->info->gen >= 12) {
-      /* TODO: Set PTE to MOCS 61 when the kernel is ready */
-      /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
-      dev->mocs.external = 3 << 1;
-      /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
-      dev->mocs.internal = 2 << 1;
+      if (dev->info->is_dg1) {
+         /* L3CC=WB */
+         dev->mocs.internal = 5 << 1;
+         /* Displayables on DG1 are free to cache in L3 since L3 is transient
+          * and flushed at bottom of each submission.
+          */
+         dev->mocs.external = 5 << 1;
+      } else {
+         /* TODO: Set PTE to MOCS 61 when the kernel is ready */
+         /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
+         dev->mocs.external = 3 << 1;
+         /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+         dev->mocs.internal = 2 << 1;
+      }
    } else if (dev->info->gen >= 9) {
       /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
       dev->mocs.external = 1 << 1;