From: lkcl <lkcl@web>
Date: Fri, 12 Aug 2022 13:36:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~882
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=793c1825a2a06bd37d48c784d70bebaaa7b3ad2c;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 4076d15e1..f89f80fda 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -37,11 +37,11 @@ add such modes without changing the behaviour of the underlying Base
 Vectorisation of Load and Store requires creation, from scalar operations,
 a number of different modes:
 
-* fixed aka "unit" stride (contiguous sequence with no gaps)
-* element strided (sequential but regularly offset, with gaps)
-* vector indexed (vector of base addresses and vector of offsets)
-* Speculative fail-first (where it makes sense to do so)
-* Structure Packing (covered in SV by [[sv/remap]]).
+* **fixed aka "unit" stride** - contiguous sequence with no gaps
+* **element strided** - sequential but regularly offset, with gaps
+* **vector indexed** - vector of base addresses and vector of offsets
+* **Speculative fail-first** - where it makes sense to do so
+* **Structure Packing** - covered in SV by [[sv/remap]] and Pack/Unpack Mode.
 
 Also included in SVP64 LD/ST is both signed and unsigned Saturation,
 as well as Element-width overrides and Twin-Predication.