From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sun, 10 Apr 2022 02:15:35 +0000 (-0500)
Subject: Put sysclk2x back under system reset control
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=793d05f2ef2e38891a4fb2ffbd6c77631fb86873;p=ls2.git

Put sysclk2x back under system reset control
---

diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index 86358d4..d588376 100644
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -219,7 +219,7 @@ class ECP5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset)
 
         # Generating sync2x (200Mhz) and init (25Mhz) from extclk
-        cd_sync2x = ClockDomain("sync2x", local=False, reset_less=True)
+        cd_sync2x = ClockDomain("sync2x", local=False)
         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
                                       local=False, reset_less=True)
         cd_init = ClockDomain("init", local=False)