From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 3 May 2016 03:27:41 +0000 (-0700)
Subject: Added GP_ABUF cell
X-Git-Tag: yosys-0.7~235^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79460208c928e62c608d71c0d6d484293835e8dc;p=yosys.git

Added GP_ABUF cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index b7dbe81a2..04bce8771 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -13,6 +13,12 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
 	assign OUT = INIT[{IN3, IN2, IN1, IN0}];
 endmodule
 
+module GP_ABUF(input wire IN, output wire OUT);
+	
+	assign OUT = IN;
+	
+endmodule
+
 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
 
 	parameter BANDWIDTH = "HIGH";