From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 15:49:37 +0000 (+0000) Subject: link unused signals to undefined X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79461a96bdd1f21aaed501c16d05a8a874d7fdb6;p=microwatt.git link unused signals to undefined to stop them appearing in LPF constraints --- diff --git a/Makefile b/Makefile index 8af9442..c6e31d4 100644 --- a/Makefile +++ b/Makefile @@ -236,7 +236,7 @@ microwatt.json: $(synth_files) $(RAM_INIT_FILE) "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) \ $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; \ read_verilog $(uart_files) $(soc_extra_v); \ - synth_ecp5 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" + synth_ecp5 -top toplevel -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" diff --git a/fpga/top-ulx3s.vhdl b/fpga/top-ulx3s.vhdl index ceecd43..43fbd0d 100644 --- a/fpga/top-ulx3s.vhdl +++ b/fpga/top-ulx3s.vhdl @@ -44,20 +44,20 @@ architecture behaviour of toplevel is signal system_clk_locked : std_ulogic; -- BRAM verilator access - signal no_bram_we : std_ulogic; - signal no_bram_re : std_ulogic; - signal no_bram_addr : std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); - signal no_bram_di : std_logic_vector(63 downto 0); - signal no_bram_do : std_logic_vector(63 downto 0); - signal no_bram_sel : std_logic_vector(7 downto 0); + signal no_bram_we : std_ulogic := 'U'; + signal no_bram_re : std_ulogic := 'U'; + signal no_bram_addr : std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0) := (others => 'U'); + signal no_bram_di : std_logic_vector(63 downto 0) := (others => 'U'); + signal no_bram_do : std_logic_vector(63 downto 0) := (others => 'U'); + signal no_bram_sel : std_logic_vector(7 downto 0) := (others => 'U'); -- for verilator debugging - signal no_nia_req: std_ulogic; - signal no_nia: std_ulogic_vector(63 downto 0); - signal no_msr_o: std_ulogic_vector(63 downto 0); - signal no_insn: std_ulogic_vector(31 downto 0); - signal no_ldst_req: std_ulogic; - signal no_ldst_addr: std_ulogic_vector(63 downto 0); + signal no_nia_req: std_ulogic := 'U'; + signal no_nia: std_ulogic_vector(63 downto 0) := (others => 'U'); + signal no_msr_o: std_ulogic_vector(63 downto 0) := (others => 'U'); + signal no_insn: std_ulogic_vector(31 downto 0) := (others => 'U'); + signal no_ldst_req: std_ulogic := 'U'; + signal no_ldst_addr: std_ulogic_vector(63 downto 0) := (others => 'U'); begin diff --git a/soc.vhdl b/soc.vhdl index c3f6a9c..b02fe12 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -268,21 +268,21 @@ architecture behaviour of soc is wishbone_data_in : in wishbone_slave_out; wishbone_data_out : out wishbone_master_out; - dmi_addr : in std_ulogic_vector(3 downto 0); - dmi_din : in std_ulogic_vector(63 downto 0); - dmi_dout : out std_ulogic_vector(63 downto 0); - dmi_req : in std_ulogic; - dmi_wr : in std_ulogic; - dmi_ack : out std_ulogic; + dmi_addr : in std_ulogic_vector(3 downto 0) := (others => 'U'); + dmi_din : in std_ulogic_vector(63 downto 0) := (others => 'U'); + dmi_dout : out std_ulogic_vector(63 downto 0) := (others => 'U'); + dmi_req : in std_ulogic := 'U'; + dmi_wr : in std_ulogic := 'U'; + dmi_ack : out std_ulogic := 'U'; ext_irq : in std_ulogic; - terminated_out : out std_logic; + terminated_out : out std_logic := 'U'; -- for verilator debugging - nia_req: out std_ulogic; - msr_o: out std_ulogic_vector(63 downto 0); - nia: out std_ulogic_vector(63 downto 0); - insn: out std_ulogic_vector(31 downto 0); - ldst_req: out std_ulogic; - ldst_addr: out std_ulogic_vector(63 downto 0) + nia_req: out std_ulogic := 'U'; + msr_o: out std_ulogic_vector(63 downto 0) := (others => 'U'); + nia: out std_ulogic_vector(63 downto 0) := (others => 'U'); + insn: out std_ulogic_vector(31 downto 0) := (others => 'U'); + ldst_req: out std_ulogic := 'U'; + ldst_addr: out std_ulogic_vector(63 downto 0) := (others => 'U') ); end component; begin