From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 23 Apr 2018 16:48:13 +0000 (+0100)
Subject: fclass std
X-Git-Tag: convert-csv-opcode-to-binary~5594
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7947455164391893d507318d7d51303d1f72191f;p=libreriscv.git

fclass std
---

diff --git a/simple_v_extension/v_comparative_analysis.mdwn b/simple_v_extension/v_comparative_analysis.mdwn
index bc5efb1f4..9736bdf74 100644
--- a/simple_v_extension/v_comparative_analysis.mdwn
+++ b/simple_v_extension/v_comparative_analysis.mdwn
@@ -450,14 +450,14 @@ and a **95%** duplication of arithmetic and floating-point operations.
 
 Exceptions are:
 
-* The Vector Misc ops: VEIDX, VFIRST, VCLASS, VPOPC
+* The Vector Misc ops: VEIDX, VFIRST, VPOPC
   and potentially more (9 control-related instructions)
-* VCLIP and VCLIPI (the only 2 opcodes not duplicated out of 46
+* VCLIP and VCLIPI (the only 2 opcodes not duplicated out of 47
   total arithmetic / floating-point operations)
 
 Table of RV32V Instructions
 
-| RV32V      | RV Equivalent (FP)   | RV Equivalent (Int) | Notes |
+| RV32V      | RV Std (FP) | RV Std (Int) | Notes |
 | -----      | ---      |         |   |
 | VADD       | FADD     | ADD     |   |
 | VSUB       | FSUB     | SUB     |   |
@@ -489,7 +489,7 @@ Table of RV32V Instructions
 | VSGNJN     | FSGNJN   |         |   |
 | VSGNJX     | FSNGJX   |         |   |
 | VSQRT      | FSQRT    |         |   |
-| VCLASS     |          |         |   |
+| VCLASS     | FCLASS   |         |   |
 | VPOPC      |          |         |   |
 | VADDI      |          | ADDI    |   |
 | VSLI       |          | SLI     |   |