From: Andreas Hansson <andreas.hansson@arm.com>
Date: Wed, 24 Feb 2016 09:16:57 +0000 (-0500)
Subject: mem: Ensure that InvalidateReq is not forwarded as ReadExReq
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7958f34797857fecf803fa4a2fcd018a8fffb640;p=gem5.git

mem: Ensure that InvalidateReq is not forwarded as ReadExReq

This patch fixes an issue where an InvalidationReq only traversed one
level of the cache hierarchy, and was subsequently turned into a
ReadExReq due to it needing writable, and the command not being
checked for explicitly.
---

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index e9b909646..724ccc7d6 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -966,7 +966,8 @@ Cache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
         // where the determination the StoreCond fails is delayed due to
         // all caches not being on the same local bus.
         cmd = MemCmd::SCUpgradeFailReq;
-    } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
+    } else if (cpu_pkt->cmd == MemCmd::WriteLineReq ||
+               cpu_pkt->cmd == MemCmd::InvalidateReq) {
         // forward as invalidate to all other caches, this gives us
         // the line in Exclusive state, and invalidates all other
         // copies