From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Tue, 13 Nov 2012 18:16:03 +0000 (-0800)
Subject: fix vector code simulation problem, turn on SR_U64
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79603491352555ab5508565845da01826cfd9430;p=riscv-isa-sim.git

fix vector code simulation problem, turn on SR_U64
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index e047126..cdcf536 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -24,7 +24,7 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id,
   : sim(*_sim), mmu(*_mmu), id(_id)
 {
   reset(true);
-  set_pcr(PCR_SR, sr | SR_EF | SR_EV);
+  set_pcr(PCR_SR, SR_U64 | SR_EF | SR_EV);
   utidx = _utidx;
 
   // microthreads don't possess their own microthreads