From: lkcl <lkcl@web>
Date: Sun, 1 May 2022 22:43:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2525
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=796c0588bfa8d9df82a4497dd865342f608ccdc0;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index e318f9127..3e59236ae 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -249,7 +249,10 @@ purpose of letting it be added onto the next BigInt digit.
     RT = lowerhalf(product)
     RC = upperhalf(product)
 
-Successive iterations thus effectively use RC as a 64-bit carry, and
+Horizontal-First Mode therefore may be applied to just this one
+instruction.
+Successive sequential iterations effectively use RC as a kind of
+64-bit carry, and
 as noted by Intel in their notes on mulx,
 `RA*RB+RC+RD` cannot overflow, so does not require
 setting an additional CA flag. We first cover the chain of