From: lkcl Date: Thu, 8 Sep 2022 15:44:31 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~613 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79712da5b0db133fe2a7a8f4b22bb52b6ecb8857;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 65fb4e507..d5899001a 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -154,7 +154,15 @@ Candidates include: * EXT005 (100% free) * brownfield space in EXT019 (25% but NOT recommended) +In order of size, for bitmanip and A/V DSP purposes: + +* QTY 3of 2-bit XO: ternlogi, crternlogi, grevlogi +* QTY 7of 3-bit XO: xpermi, binlut, grevlog, swizzle-mv/fmv, bitmask, bmrevi +* QTY 8of 5/6-bit: xpermi, bincrflut, fmvis, fishmv, bmrev, Galois Field +* + +Additionally [^extend]: Prefix opcode space **must** be reserved in advance to do so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2 [^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations. -[^pseudorewrite] elwidth overrides does however mean that all SFS / SFFS pseudocode will need rewriting to be in terms of XLEN. This has the indirect side-effect of automatically making a 32-bit Scalar Power ISA Specification possible, as well as a future 128-bit one (Cross-reference: RISC-V RV32 and RV128) +[^pseudorewrite]: elwidth overrides does however mean that all SFS / SFFS pseudocode will need rewriting to be in terms of XLEN. This has the indirect side-effect of automatically making a 32-bit Scalar Power ISA Specification possible, as well as a future 128-bit one (Cross-reference: RISC-V RV32 and RV128)