From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 18 Mar 2013 17:44:58 +0000 (+0100)
Subject: generic_platform: do not create clock domains during Verilog conversion
X-Git-Tag: 24jan2021_ls180~2099^2~443^2~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=797411c1a9bc0c0a90a0d0cb0ed867d3bb7c12ee;p=litex.git

generic_platform: do not create clock domains during Verilog conversion
---

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index d3fe50b2..fcbe7ba3 100644
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -214,7 +214,8 @@ class GenericPlatform:
 			else:
 				frag = fragment
 			# generate Verilog
-			src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, **kwargs)
+			src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
+				return_ns=True, create_clock_domains=False, **kwargs)
 			# resolve signal names in constraints
 			sc = self.constraint_manager.get_sig_constraints()
 			named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]