From: lkcl <lkcl@web>
Date: Mon, 12 Sep 2022 16:16:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~464
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=798fcfe87687f1e911f87c0ab2a5d2d57ccf60cb;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index f7415503a..18c8d0319 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -65,9 +65,6 @@ Other modes are still applicable and include:
 for analysing a Vector of Condition Register Fields
 and reducing it to one
 single Condition Register Field.
-* **Pack/Unpack Mode**.
-  Like VSX `vpack` and `vunpack` the source and destination
-  elements are reordered.
 
 Predicate-result does not make any sense because
 when Rc=1 a co-result is created (a CR Field). Testing the co-result
@@ -84,6 +81,7 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 |sz |SNZ| 0 RG  |   0 | dz  /   | simple mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
 |zz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
+|zz |SNZ| 0 RG  |   1 | /   1   | reserved   |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |