From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 18 Mar 2011 00:20:19 +0000 (-0500)
Subject: O3: Send instruction back to fetch on squash to seed predecoder correctly.
X-Git-Tag: stable_2012_02_02~473^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=799c3da8d0086bfdfbae532e05018828387e4497;p=gem5.git

O3: Send instruction back to fetch on squash to seed predecoder correctly.
---

diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index a8788051f..2f8c4c2ef 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -76,6 +76,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh
index a99e38ce7..511bc29bc 100644
--- a/src/arch/arm/predecoder.hh
+++ b/src/arch/arm/predecoder.hh
@@ -83,6 +83,12 @@ namespace ArmISA
             predAddrValid = false;
         }
 
+        void reset(const ExtMachInst &old_emi)
+        {
+            reset();
+            itstate = old_emi.newItstate;
+        }
+
         Predecoder(ThreadContext * _tc) :
             tc(_tc), data(0)
         {
diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh
index 4220b768c..110493cc5 100644
--- a/src/arch/mips/predecoder.hh
+++ b/src/arch/mips/predecoder.hh
@@ -75,6 +75,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     //Use this to give data to the predecoder. This should be used
     //when there is control flow.
     void
diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh
index 8b1089095..c10bc51bf 100644
--- a/src/arch/power/predecoder.hh
+++ b/src/arch/power/predecoder.hh
@@ -82,6 +82,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index 670c547d0..082adeb72 100644
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -68,12 +68,19 @@ class Predecoder
     }
 
     void process() {}
+
     void
     reset()
     {
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 5c67e28e1..790453b98 100644
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -174,6 +174,12 @@ namespace X86ISA
             state = ResetState;
         }
 
+        void
+        reset(const ExtMachInst &old_emi)
+        {
+            reset();
+        }
+
         ThreadContext * getTC()
         {
             return tc;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2d3bc3f72..4088f2399 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -808,8 +808,9 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     }
 
     // Squash Throughout Pipeline
-    InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
-    fetch.squash(0, squash_seq_num, tid);
+    DynInstPtr inst = commit.rob->readHeadInst(tid);
+    InstSeqNum squash_seq_num = inst->seqNum;
+    fetch.squash(0, squash_seq_num, inst, tid);
     decode.squash(tid);
     rename.squash(squash_seq_num, tid);
     iew.squash(tid);
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index c51658104..4a4ac0902 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -312,8 +312,8 @@ class DefaultFetch
      * remove any instructions that are not in the ROB. The source of this
      * squash should be the commit stage.
      */
-    void squash(const TheISA::PCState &newPC,
-                const InstSeqNum &seq_num, ThreadID tid);
+    void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
+                DynInstPtr &squashInst, ThreadID tid);
 
     /** Ticks the fetch stage, processing all inputs signals and fetching
      * as many instructions as possible.
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 5f9be039f..6c1ac456d 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -815,11 +815,14 @@ DefaultFetch<Impl>::updateFetchStatus()
 template <class Impl>
 void
 DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
-                           const InstSeqNum &seq_num, ThreadID tid)
+                           const InstSeqNum &seq_num, DynInstPtr &squashInst,
+                           ThreadID tid)
 {
     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
 
     doSquash(newPC, tid);
+    if (squashInst)
+        predecoder.reset(squashInst->staticInst->machInst);
 
     // Tell the CPU to remove any instructions that are not in the ROB.
     cpu->removeInstsNotInROB(tid);
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index f619dd11b..60aa857ac 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *