From: Jacob Lifshay Date: Tue, 3 May 2022 08:30:50 +0000 (-0700) Subject: add Rc to ternlogi X-Git-Tag: sv_maxu_works-initial~447 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79b540bb5d8f8ba139f56ff1e8010bde24df3d22;p=openpower-isa.git add Rc to ternlogi --- diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn index b2b0ad8b..d1521a76 100644 --- a/openpower/isa/bitmanip.mdwn +++ b/openpower/isa/bitmanip.mdwn @@ -6,6 +6,7 @@ TLI-Form * ternlogi RT, RA, RB, TLI +* ternlogi. RT, RA, RB, TLI Pseudo-code: @@ -17,7 +18,7 @@ Pseudo-code: Special Registers Altered: - None + CR0 (if Rc=1) # Generalized Bit-Reverse diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index d4b5075f..eb962688 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -288,8 +288,8 @@ | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO | / | # 1.6.34 TLI-FORM - |0 |6 |11 |16 |21 |29 | - | PO | RT | RA | RB | TLI | XO | + |0 |6 |11 |16 |21 |29 |31 | + | PO | RT | RA | RB | TLI | XO |Rc | # 1.6.28 Instruction Fields A (6) @@ -684,7 +684,7 @@ 1 Set Condition Register Field 0 or Field 1 as described in Section 2.3.1, 'Condition Regis- ter' on page 30. - Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL, XB + Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL, XB, TLI RIC (12:13) Field used to specify what types of entries to inval- idate for tlbie[l]. diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv index c0260dbf..071cc999 100644 --- a/openpower/isatables/minor_5.csv +++ b/openpower/isatables/minor_5.csv @@ -1,5 +1,5 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 ---------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg +--------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg 0010010110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,grev,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -011010110-,SHIFT_ROT,OP_GREV,RA,CONST_XBI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,grevi,XB,,1,unofficial until submitted and approved/renumbered by the opf isa wg 0010110110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,grevw,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 8a070630..afa3f76e 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1268,8 +1268,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): illegal = False ins_name = 'ffadds' - if asmop == 'ternlogi' \ - or re.fullmatch(r'grevw?i?\.?', asmop or ''): + if re.fullmatch(r'ternlogi\.?|grevw?i?\.?', asmop or ''): illegal = False ins_name = asmop diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index b43f317e..26c2e278 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -584,7 +584,7 @@ class DecodeOE(Elaboratable): MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC, MicrOp.OP_LOAD, MicrOp.OP_STORE, MicrOp.OP_RLCL, MicrOp.OP_RLCR, - MicrOp.OP_EXTSWSLI, MicrOp.OP_GREV): + MicrOp.OP_EXTSWSLI, MicrOp.OP_GREV, MicrOp.OP_TERNLOG): pass # all other ops decode OE field diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 7b52769d..b1954160 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -283,20 +283,22 @@ class SVP64Asm: # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG # however we are out of space with opcode 22 - if opcode == 'ternlogi': + if opcode in ('ternlogi', 'ternlogi.'): po = 5 xo = 0 rt = int(fields[0]) ra = int(fields[1]) rb = int(fields[2]) imm = int(fields[3]) + rc = '.' in opcode instr = po instr = (instr << 5) | rt instr = (instr << 5) | ra instr = (instr << 5) | rb instr = (instr << 8) | imm - instr = (instr << 3) | xo - asm = f"ternlogi {rt}, {ra}, {rb}, {imm}" + instr = (instr << 2) | xo + instr = (instr << 1) | rc + asm = f"{opcode} {rt}, {ra}, {rb}, {imm}" yield f".4byte {hex(instr)} # {asm}" return diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py index 0fcb0d71..88bdd057 100644 --- a/src/openpower/test/bitmanip/bitmanip_cases.py +++ b/src/openpower/test/bitmanip/bitmanip_cases.py @@ -7,8 +7,9 @@ from nmutil.sim_util import hash_256 class BitManipTestCase(TestAccumulatorBase): - def do_case_ternlogi(self, rt, ra, rb, imm): - lst = [f"ternlogi 3, 4, 5, {imm}"] + def do_case_ternlogi(self, rc, rt, ra, rb, imm): + rc_dot = "." if rc else "" + lst = [f"ternlogi{rc_dot} 3, 4, 5, {imm}"] initial_regs = [0] * 32 rt %= 2 ** 64 ra %= 2 ** 64 @@ -32,6 +33,13 @@ class BitManipTestCase(TestAccumulatorBase): e.intregs[3] = expected e.intregs[4] = ra e.intregs[5] = rb + if rc: + if expected & 2 ** 63: # sign extend + expected -= 2 ** 64 + eq = expected == 0 + gt = expected > 0 + lt = expected < 0 + e.crregs[0] = (eq << 1) | (gt << 2) | (lt << 3) self.add_case(Program(lst, bigendian), initial_regs, expected=e) def do_case_grev(self, w, is_imm, ra, rb): @@ -65,20 +73,27 @@ class BitManipTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, expected=e) def case_ternlogi_0(self): - self.do_case_ternlogi(0x8000_0000_FFFF_0000, + self.do_case_ternlogi(False, + 0x8000_0000_FFFF_0000, + 0x8000_0000_FF00_FF00, + 0x8000_0000_F0F0_F0F0, 0x80) + self.do_case_ternlogi(True, + 0x8000_0000_FFFF_0000, 0x8000_0000_FF00_FF00, 0x8000_0000_F0F0_F0F0, 0x80) def case_ternlogi_FF(self): - self.do_case_ternlogi(0, 0, 0, 0xFF) + self.do_case_ternlogi(False, 0, 0, 0, 0xFF) + self.do_case_ternlogi(True, 0, 0, 0, 0xFF) def case_ternlogi_random(self): for i in range(100): + rc = bool(hash_256(f"ternlogi rc {i}") & 1) imm = hash_256(f"ternlogi imm {i}") & 0xFF rt = hash_256(f"ternlogi rt {i}") % 2 ** 64 ra = hash_256(f"ternlogi ra {i}") % 2 ** 64 rb = hash_256(f"ternlogi rb {i}") % 2 ** 64 - self.do_case_ternlogi(rt, ra, rb, imm) + self.do_case_ternlogi(rc, rt, ra, rb, imm) def case_grev_random(self): for i in range(100):