From: Francisco Jerez Date: Thu, 15 Dec 2016 21:34:02 +0000 (-0800) Subject: anv: Fix uniform and storage buffer offset alignment limits. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79d08ed3d21bef21881303f320706ebb2098a50a;p=mesa.git anv: Fix uniform and storage buffer offset alignment limits. This fixes a regression in a bunch of image store vulkan CTS tests from commit ad38ba113491869ab0dffed937f7b3dd50e8a735, which started using OWORD block read messages to implement UBO loads. The reason for the failure is that we were giving bogus buffer alignment limits to the application (1B), so the CTS would happily come back with descriptor sets pointing at not even word-aligned uniform buffer addresses. Surprisingly the sampler messages used to fetch pull constants before that commit were able to cope with the non-texel aligned addresses, but the dataport messages used to fetch pull constants after that commit and the ones used to access storage buffers (before and after the same commit) aren't as permissive with unaligned addresses. Cc: Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99097 Reported-by: Mark Janes Reviewed-by: Jason Ekstrand --- diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index e3d278df733..9245e5c878b 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -582,8 +582,8 @@ void anv_GetPhysicalDeviceProperties( .viewportSubPixelBits = 13, /* We take a float? */ .minMemoryMapAlignment = 4096, /* A page */ .minTexelBufferOffsetAlignment = 1, - .minUniformBufferOffsetAlignment = 1, - .minStorageBufferOffsetAlignment = 1, + .minUniformBufferOffsetAlignment = 16, + .minStorageBufferOffsetAlignment = 4, .minTexelOffset = -8, .maxTexelOffset = 7, .minTexelGatherOffset = -32,