From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 23 Dec 2021 16:56:21 +0000 (+0000)
Subject: add ability to set the reset values of RegFileArray
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79d09c90765b810424a735a60829abbb4b7a2ce2;p=soc.git

add ability to set the reset values of RegFileArray
---

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index c3f33393..e1274b4b 100644
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -107,13 +107,17 @@ class RegFileArray(Elaboratable):
         and read-en signals (per port).
     """
 
-    def __init__(self, width, depth, synced=True, fwd_bus_mode=True):
+    def __init__(self, width, depth, synced=True, fwd_bus_mode=True,
+                                     resets=None):
+        if resets is None:
+            resets = [0] * depth
         self.synced = synced
         self.width = width
         self.depth = depth
         self.regs = Array(Register(width, synced=synced,
-                                   writethru=fwd_bus_mode) \
-                          for _ in range(self.depth))
+                                   writethru=fwd_bus_mode,
+                                   resetval=rst) \
+                          for rst in resets)
         self._rdports = []
         self._wrports = []