From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 12 Jan 2020 01:26:25 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
X-Git-Tag: working-ls180~849^2~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79db12f238b2f8c5d547ea731a056f98d89bc4b9;p=yosys.git

Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
---

79db12f238b2f8c5d547ea731a056f98d89bc4b9
diff --cc backends/aiger/xaiger.cc
index beaed696d,7ee5058ae..212e1e561
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@@ -523,36 -612,106 +524,44 @@@ struct XAigerWrite
  		//	write_o_buffer(0);
  
  		if (!box_list.empty() || !ff_bits.empty()) {
 -			RTLIL::Module *holes_module = module->design->addModule("$__holes__");
 +			RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
  			log_assert(holes_module);
  
- 			dict<IdString, Cell*> cell_cache;
 -			dict<IdString, std::tuple<Cell*,int,int,int>> cell_cache;
++			dict<IdString, std::tuple<int,int,int>> cell_cache;
  
 -			int port_id = 1;
  			int box_count = 0;
  			for (auto cell : box_list) {
 -				RTLIL::Module* orig_box_module = module->design->module(cell->type);
 -				log_assert(orig_box_module);
 -				IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
 -				RTLIL::Module* box_module = module->design->module(derived_name);
 +				log_assert(cell);
  
 -				auto r = cell_cache.insert(derived_name);
 +				RTLIL::Module* box_module = module->design->module(cell->type);
 +				log_assert(box_module);
 +
- 				int box_inputs = 0, box_outputs = 0;
- 				for (auto port_name : box_module->ports) {
- 					RTLIL::Wire *w = box_module->wire(port_name);
- 					log_assert(w);
- 					if (w->port_input)
- 						box_inputs += GetSize(w);
- 					if (w->port_output)
- 						box_outputs += GetSize(w);
- 				}
++				auto r = cell_cache.insert(cell->type);
+ 				auto &v = r.first->second;
+ 				if (r.second) {
 -					if (box_module->has_processes())
 -						Pass::call_on_module(module->design, box_module, "proc");
 -
+ 					int box_inputs = 0, box_outputs = 0;
 -					if (box_module->get_bool_attribute("\\whitebox")) {
 -						auto holes_cell = holes_module->addCell(cell->name, derived_name);
 -						for (auto port_name : box_ports.at(cell->type)) {
 -							RTLIL::Wire *w = box_module->wire(port_name);
 -							log_assert(w);
 -							log_assert(!w->port_input || !w->port_output);
 -							auto &conn = holes_cell->connections_[port_name];
 -							if (w->port_input) {
 -								for (int i = 0; i < GetSize(w); i++) {
 -									box_inputs++;
 -									RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
 -									if (!holes_wire) {
 -										holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
 -										holes_wire->port_input = true;
 -										holes_wire->port_id = port_id++;
 -										holes_module->ports.push_back(holes_wire->name);
 -									}
 -									conn.append(holes_wire);
 -								}
 -							}
 -							else if (w->port_output) {
 -								box_outputs += GetSize(w);
 -								conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
 -							}
 -						}
 -
 -						// For flops only, create an extra 1-bit input that drives a new wire
 -						//   called "<cell>.abc9_ff.Q" that is used below
 -						if (box_module->get_bool_attribute("\\abc9_flop")) {
 -							box_inputs++;
 -							Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
 -							if (!holes_wire) {
 -								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
 -								holes_wire->port_input = true;
 -								holes_wire->port_id = port_id++;
 -								holes_module->ports.push_back(holes_wire->name);
 -							}
 -							Wire *Q = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
 -							holes_module->connect(Q, holes_wire);
 -						}
 -
 -						std::get<0>(v) = holes_cell;
 -					}
 -					else {
 -						for (auto port_name : box_ports.at(cell->type)) {
 -							RTLIL::Wire *w = box_module->wire(port_name);
 -							log_assert(w);
 -							log_assert(!w->port_input || !w->port_output);
 -							if (w->port_input)
 -								box_inputs += GetSize(w);
 -							else if (w->port_output)
 -								box_outputs += GetSize(w);
 -						}
 -						log_assert(std::get<0>(v) == nullptr);
++					for (auto port_name : box_module->ports) {
++						RTLIL::Wire *w = box_module->wire(port_name);
++						log_assert(w);
++						if (w->port_input)
++							box_inputs += GetSize(w);
++						if (w->port_output)
++							box_outputs += GetSize(w);
+ 					}
  
- 				// For flops only, create an extra 1-bit input that drives a new wire
- 				//   called "<cell>.abc9_ff.Q" that is used below
- 				if (box_module->get_bool_attribute("\\abc9_flop"))
- 					box_inputs++;
 -					std::get<1>(v) = box_inputs;
 -					std::get<2>(v) = box_outputs;
 -					std::get<3>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
 -				}
++					// For flops only, create an extra 1-bit input that drives a new wire
++					//   called "<cell>.abc9_ff.Q" that is used below
++					if (box_module->get_bool_attribute("\\abc9_flop"))
++					    box_inputs++;
+ 
 -				auto holes_cell = std::get<0>(v);
 -				for (auto port_name : box_ports.at(cell->type)) {
 -					RTLIL::Wire *w = box_module->wire(port_name);
 -					log_assert(w);
 -					if (!w->port_output)
 -						continue;
 -					Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
 -					holes_wire->port_output = true;
 -					holes_wire->port_id = port_id++;
 -					holes_module->ports.push_back(holes_wire->name);
 -					if (holes_cell) // whitebox
 -						holes_module->connect(holes_wire, holes_cell->getPort(port_name));
 -					else // blackbox
 -						holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
++					std::get<0>(v) = box_inputs;
++					std::get<1>(v) = box_outputs;
++					std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
+ 				}
  
- 				write_h_buffer(box_inputs);
- 				write_h_buffer(box_outputs);
- 				write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int());
++				write_h_buffer(std::get<0>(v));
+ 				write_h_buffer(std::get<1>(v));
+ 				write_h_buffer(std::get<2>(v));
 -				write_h_buffer(std::get<3>(v));
  				write_h_buffer(box_count++);
  			}
  
diff --cc passes/techmap/abc9.cc
index 939eff021,471c11a80..30b62dc79
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@@ -167,88 -924,120 +167,90 @@@ struct Abc9Pass : public ScriptPas
  		}
  		extra_args(args, argidx, design);
  
 -		rewrite_filename(script_file);
 -		if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
 -			script_file = std::string(pwd) + "/" + script_file;
 +		log_header(design, "Executing ABC9 pass.\n");
  
 -		// handle -lut / -luts args
 -		if (!lut_arg.empty()) {
 -			string arg = lut_arg;
 -			if (arg.find_first_not_of("0123456789:") == std::string::npos) {
 -				size_t pos = arg.find_first_of(':');
 -				int lut_mode = 0, lut_mode2 = 0;
 -				if (pos != string::npos) {
 -					lut_mode = atoi(arg.substr(0, pos).c_str());
 -					lut_mode2 = atoi(arg.substr(pos+1).c_str());
 -				} else {
 -					lut_mode = atoi(arg.c_str());
 -					lut_mode2 = lut_mode;
 -				}
 -				lut_costs.clear();
 -				for (int i = 0; i < lut_mode; i++)
 -					lut_costs.push_back(1);
 -				for (int i = lut_mode; i < lut_mode2; i++)
 -					lut_costs.push_back(2 << (i - lut_mode));
 -			}
 -			else {
 -				lut_file = arg;
 -				rewrite_filename(lut_file);
 -				if (!lut_file.empty() && !is_absolute_path(lut_file) && lut_file[0] != '+')
 -					lut_file = std::string(pwd) + "/" + lut_file;
 -			}
 -		}
 -		if (!luts_arg.empty()) {
 -			lut_costs.clear();
 -			for (auto &tok : split_tokens(luts_arg, ",")) {
 -				auto parts = split_tokens(tok, ":");
 -				if (GetSize(parts) == 0 && !lut_costs.empty())
 -					lut_costs.push_back(lut_costs.back());
 -				else if (GetSize(parts) == 1)
 -					lut_costs.push_back(atoi(parts.at(0).c_str()));
 -				else if (GetSize(parts) == 2)
 -					while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
 -						lut_costs.push_back(atoi(parts.at(1).c_str()));
 -				else
 -					log_cmd_error("Invalid -luts syntax.\n");
 -			}
 -		}
 -
 -		// ABC expects a box file for XAIG
 -		if (box_file.empty())
 -		    box_file = "+/dummy.box";
 +		run_script(design, run_from, run_to);
 +	}
  
 -		rewrite_filename(box_file);
 -		if (!box_file.empty() && !is_absolute_path(box_file) && box_file[0] != '+')
 -		    box_file = std::string(pwd) + "/" + box_file;
 +	void script() YS_OVERRIDE
 +	{
 +		if (check_label("pre")) {
 +			run("scc -set_attr abc9_scc_id {}");
 +			if (help_mode)
 +				run("abc9_ops -break_scc -prep_holes [-dff]", "(option for -dff)");
 +			else
 +				run("abc9_ops -break_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
 +			run("select -set abc9_holes A:abc9_holes");
 +			run("flatten -wb @abc9_holes");
++run("dump @abc9_holes");
 +			run("techmap @abc9_holes");
- 			run("aigmap");
 +			if (dff_mode || help_mode)
 +				run("abc9_ops -prep_dff", "(only if -dff)");
 +			run("opt -purge @abc9_holes");
++run("dump @abc9_holes");
++			run("aigmap");
 +			run("wbflip @abc9_holes");
 +		}
  
 -		SigMap assign_map;
 -		CellTypes ct(design);
 -		for (auto module : design->selected_modules())
 -		{
 -			if (module->processes.size() > 0) {
 -				log("Skipping module %s as it contains processes.\n", log_id(module));
 -				continue;
 +		if (check_label("map")) {
 +			if (help_mode) {
 +				run("foreach module in selection");
 +				run("    write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
 +				run("    abc9_exe -cwd <abc-temp-dir> [options]");
 +				run("    read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
 +				run("    abc9_ops -reintegrate");
  			}
 -			log_assert(!module->attributes.count(ID(abc9_box_id)));
 -
 -			if (!design->selected_whole_module(module))
 -				log_error("Can't handle partially selected module %s!\n", log_id(module));
 -
 -			assign_map.set(module);
 -
 -			typedef SigSpec clkdomain_t;
 -			dict<clkdomain_t, int> clk_to_mergeability;
 +			else {
 +				auto selected_modules = active_design->selected_modules();
 +				active_design->selection_stack.emplace_back(false);
  
 -			if (dff_mode)
 -				for (auto cell : module->cells()) {
 -					if (cell->type != "$__ABC9_FF_")
 +				for (auto mod : selected_modules) {
 +					if (mod->processes.size() > 0) {
 +						log("Skipping module %s as it contains processes.\n", log_id(mod));
  						continue;
 +					}
 +					log_assert(!mod->attributes.count(ID(abc9_box_id)));
 +
 +					active_design->selection().select(mod);
 +
 +					if (!active_design->selected_whole_module(mod))
 +						log_error("Can't handle partially selected module %s!\n", log_id(mod));
 +
 +					std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
 +					if (!cleanup)
 +						tempdir_name[0] = tempdir_name[4] = '_';
 +					tempdir_name = make_temp_dir(tempdir_name);
 +
 +					run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
 +
 +					int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
 +					log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
 +							active_design->scratchpad_get_int("write_xaiger.num_ands"),
 +							active_design->scratchpad_get_int("write_xaiger.num_wires"),
 +							active_design->scratchpad_get_int("write_xaiger.num_inputs"),
 +							num_outputs);
 +					if (num_outputs) {
 +						run(stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str()));
 +						run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod->name), tempdir_name.c_str(), tempdir_name.c_str()));
 +						run("abc9_ops -reintegrate");
 +					}
 +					else
 +						log("Don't call ABC as there is nothing to map.\n");
  
 -					Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
 -					if (abc9_clock_wire == NULL)
 -						log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 -					SigSpec abc9_clock = assign_map(abc9_clock_wire);
 -
 -					clkdomain_t key(abc9_clock);
 -
 -					auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
 -					auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
 -					log_assert(r2.second);
 +					if (cleanup) {
 +						log("Removing temp directory.\n");
 +						remove_directory(tempdir_name);
 +					}
  
 -					Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
 -					if (abc9_init_wire == NULL)
 -						log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 -					log_assert(GetSize(abc9_init_wire) == 1);
 -					SigSpec abc9_init = assign_map(abc9_init_wire);
 -					if (!abc9_init.is_fully_const())
 -						log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 -					r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
 -					log_assert(r2.second);
 -				}
 -			else
 -				for (auto cell : module->cells()) {
 -					auto inst_module = design->module(cell->type);
 -					if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
 -						continue;
 -					cell->set_bool_attribute("\\abc9_keep");
 +					active_design->selection().selected_modules.clear();
  				}
  
 -			design->selected_active_module = module->name.str();
 -			abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, dff_mode,
 -					delay_target, lutin_shared, fast_mode, show_tempdir,
 -					box_file, lut_file, wire_delay);
 -			design->selected_active_module.clear();
 +				active_design->selection_stack.pop_back();
 +			}
  		}
  
 -		log_pop();
 +		if (check_label("post"))
 +			run("abc9_ops -unbreak_scc");
  	}
  } Abc9Pass;
  
diff --cc passes/techmap/abc9_ops.cc
index 6f089447e,000000000..cc22fd474
mode 100644,000000..100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@@ -1,879 -1,0 +1,879 @@@
 +/*
 + *  yosys -- Yosys Open SYnthesis Suite
 + *
 + *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 + *                2019  Eddie Hung <eddie@fpgeh.com>
 + *
 + *  Permission to use, copy, modify, and/or distribute this software for any
 + *  purpose with or without fee is hereby granted, provided that the above
 + *  copyright notice and this permission notice appear in all copies.
 + *
 + *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 + *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 + *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 + *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 + *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 + *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 + *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 + *
 + */
 +
 +#include "kernel/register.h"
 +#include "kernel/sigtools.h"
 +#include "kernel/utils.h"
 +#include "kernel/celltypes.h"
 +
 +USING_YOSYS_NAMESPACE
 +PRIVATE_NAMESPACE_BEGIN
 +
 +int map_autoidx;
 +
 +inline std::string remap_name(RTLIL::IdString abc9_name)
 +{
 +	return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
 +}
 +
 +void break_scc(RTLIL::Module *module)
 +{
 +	// For every unique SCC found, (arbitrarily) find the first
 +	//   cell in the component, and convert all wires driven by
 +	//   its output ports into a new PO, and drive its previous
 +	//   sinks with a new PI
 +	pool<RTLIL::Const> ids_seen;
 +	for (auto cell : module->cells()) {
 +		auto it = cell->attributes.find(ID(abc9_scc_id));
 +		if (it == cell->attributes.end())
 +			continue;
 +		auto r = ids_seen.insert(it->second);
 +		cell->attributes.erase(it);
 +		if (!r.second)
 +			continue;
 +		for (auto &c : cell->connections_) {
 +			if (c.second.is_fully_const()) continue;
 +			if (cell->output(c.first)) {
 +				SigBit b = c.second.as_bit();
 +				Wire *w = b.wire;
 +				if (w->port_input) {
 +					// In this case, hopefully the loop break has been already created
 +					// Get the non-prefixed wire
 +					Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str()));
 +					log_assert(wo != nullptr);
 +					log_assert(wo->port_output);
 +					log_assert(b.offset < GetSize(wo));
 +					c.second = RTLIL::SigBit(wo, b.offset);
 +				}
 +				else {
 +					// Create a new output/input loop break
 +					w->port_input = true;
 +					w = module->wire(stringf("%s.abco", w->name.c_str()));
 +					if (!w) {
 +						w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire));
 +						w->port_output = true;
 +					}
 +					else {
 +						log_assert(w->port_input);
 +						log_assert(b.offset < GetSize(w));
 +					}
 +					w->set_bool_attribute(ID(abc9_scc_break));
 +					c.second = RTLIL::SigBit(w, b.offset);
 +				}
 +			}
 +		}
 +	}
 +
 +	module->fixup_ports();
 +}
 +
 +void unbreak_scc(RTLIL::Module *module)
 +{
 +	// Now 'unexpose' those wires by undoing
 +	// the expose operation -- remove them from PO/PI
 +	// and re-connecting them back together
 +	for (auto wire : module->wires()) {
 +		auto it = wire->attributes.find(ID(abc9_scc_break));
 +		if (it != wire->attributes.end()) {
 +			wire->attributes.erase(it);
 +			log_assert(wire->port_output);
 +			wire->port_output = false;
 +			std::string name = wire->name.str();
 +			RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
 +			log_assert(i_wire);
 +			log_assert(i_wire->port_input);
 +			i_wire->port_input = false;
 +			module->connect(i_wire, wire);
 +		}
 +	}
 +	module->fixup_ports();
 +}
 +
 +void prep_dff(RTLIL::Module *module)
 +{
 +	auto design = module->design;
 +	log_assert(design);
 +
 +	SigMap assign_map(module);
 +
 +	typedef SigSpec clkdomain_t;
 +	dict<clkdomain_t, int> clk_to_mergeability;
 +
 +	for (auto cell : module->cells()) {
 +		if (cell->type != "$__ABC9_FF_")
 +			continue;
 +
 +		Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
 +		if (abc9_clock_wire == NULL)
 +			log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 +		SigSpec abc9_clock = assign_map(abc9_clock_wire);
 +
 +		clkdomain_t key(abc9_clock);
 +
 +		auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
 +		auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
 +		log_assert(r2.second);
 +
 +		Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
 +		if (abc9_init_wire == NULL)
 +			log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 +		log_assert(GetSize(abc9_init_wire) == 1);
 +		SigSpec abc9_init = assign_map(abc9_init_wire);
 +		if (!abc9_init.is_fully_const())
 +			log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 +		r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
 +		log_assert(r2.second);
 +	}
 +
 +	RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
 +	if (holes_module) {
- 		dict<SigSig, SigSig> replace;
++		SigMap sigmap(holes_module);
++
++		dict<SigSpec, SigSpec> replace;
 +		for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
 +			auto cell = it->second;
 +			if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
 +						"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
 +				SigBit D = cell->getPort("\\D");
 +				SigBit Q = cell->getPort("\\Q");
- 				// Remove the DFF cell from what needs to be a combinatorial box
++				// Remove the $_DFF_* cell from what needs to be a combinatorial box
 +				it = holes_module->cells_.erase(it);
 +				Wire *port;
 +				if (GetSize(Q.wire) == 1)
 +					port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
 +				else
 +					port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
 +				log_assert(port);
- 				// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
- 				//   in order to extract the combinatorial control logic that feeds the box
++				// Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
++				//   in order to extract just the combinatorial control logic that feeds the box
 +				//   (i.e. clock enable, synchronous reset, etc.)
- 				replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
++				replace.insert(std::make_pair(Q,D));
 +				// Since `flatten` above would have created wires named "<cell>.Q",
 +				//   extract the pre-techmap cell name
 +				auto pos = Q.wire->name.str().rfind(".");
 +				log_assert(pos != std::string::npos);
 +				IdString driver = Q.wire->name.substr(0, pos);
 +				// And drive the signal that was previously driven by "DFF.Q" (typically
 +				//   used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
- 				//   wire (which itself is driven an input port) we inserted above
++				//   wire (which itself is driven an by input port) we inserted above
 +				Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
 +				log_assert(currQ);
 +				holes_module->connect(Q, currQ);
 +			}
 +			else
 +				++it;
 +		}
 +
 +		for (auto &conn : holes_module->connections_)
- 			conn = replace.at(conn, conn);
++			conn.second = replace.at(sigmap(conn.second), conn.second);
 +	}
 +}
 +
 +void prep_holes(RTLIL::Module *module, bool dff)
 +{
 +	auto design = module->design;
 +	log_assert(design);
 +
 +	SigMap sigmap(module);
 +
 +	dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 +	TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
 +	bool abc9_box_seen = false;
 +
 +	for (auto cell : module->cells()) {
 +		if (cell->type == "$__ABC9_FF_")
 +			continue;
 +
 +		auto inst_module = module->design->module(cell->type);
 +		bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
 +		bool abc9_flop = false;
 +		if (abc9_box) {
 +			abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
 +			if (abc9_flop && !dff)
 +				continue;
 +			abc9_box_seen = abc9_box;
 +		}
 +		else if (!yosys_celltypes.cell_known(cell->type))
 +			continue;
 +
 +		for (auto conn : cell->connections()) {
 +			if (cell->input(conn.first))
 +				for (auto bit : sigmap(conn.second))
 +					bit_users[bit].insert(cell->name);
 +
 +			if (cell->output(conn.first) && !abc9_flop)
 +				for (auto bit : sigmap(conn.second))
 +					bit_drivers[bit].insert(cell->name);
 +		}
 +
 +		toposort.node(cell->name);
 +	}
 +
 +	if (!abc9_box_seen)
 +		return;
 +
 +	for (auto &it : bit_users)
 +		if (bit_drivers.count(it.first))
 +			for (auto driver_cell : bit_drivers.at(it.first))
 +			for (auto user_cell : it.second)
 +				toposort.edge(driver_cell, user_cell);
 +
 +	if (ys_debug(1))
 +		toposort.analyze_loops = true;
 +
 +	bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
 +
 +	if (ys_debug(1)) {
 +		unsigned i = 0;
 +		for (auto &it : toposort.loops) {
 +			log("  loop %d\n", i++);
 +			for (auto cell_name : it) {
 +				auto cell = module->cell(cell_name);
 +				log_assert(cell);
 +				log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
 +			}
 +		}
 +	}
 +
 +	log_assert(no_loops);
 +
 +	vector<Cell*> box_list;
 +	for (auto cell_name : toposort.sorted) {
 +		RTLIL::Cell *cell = module->cell(cell_name);
 +		log_assert(cell);
 +
 +		RTLIL::Module* box_module = design->module(cell->type);
 +		if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
 +			continue;
 +
 +		bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
 +
 +		// Fully pad all unused input connections of this box cell with S0
 +		// Fully pad all undriven output connections of this box cell with anonymous wires
 +		for (const auto &port_name : box_module->ports) {
 +			RTLIL::Wire* w = box_module->wire(port_name);
 +			log_assert(w);
 +			auto it = cell->connections_.find(port_name);
 +			if (w->port_input) {
 +				RTLIL::SigSpec rhs;
 +				if (it != cell->connections_.end()) {
 +					if (GetSize(it->second) < GetSize(w))
 +						it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
 +					rhs = it->second;
 +				}
 +				else {
 +					rhs = RTLIL::SigSpec(State::S0, GetSize(w));
 +					cell->setPort(port_name, rhs);
 +				}
 +			}
 +			if (w->port_output) {
 +				RTLIL::SigSpec rhs;
 +				auto it = cell->connections_.find(w->name);
 +				if (it != cell->connections_.end()) {
 +					if (GetSize(it->second) < GetSize(w))
 +						it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
 +					rhs = it->second;
 +				}
 +				else {
 +					Wire *wire = module->addWire(NEW_ID, GetSize(w));
 +					if (blackbox)
 +						wire->set_bool_attribute(ID(abc9_padding));
 +					rhs = wire;
 +					cell->setPort(port_name, rhs);
 +				}
 +			}
 +		}
 +
 +		cell->attributes["\\abc9_box_seq"] = box_list.size();
 +		box_list.emplace_back(cell);
 +	}
 +	log_assert(!box_list.empty());
 +
 +	RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
 +	log_assert(holes_module);
 +	holes_module->set_bool_attribute("\\abc9_holes");
 +
 +	dict<IdString, Cell*> cell_cache;
 +	dict<IdString, std::vector<IdString>> box_ports;
 +
 +	int port_id = 1;
 +	for (auto cell : box_list) {
 +		RTLIL::Module* orig_box_module = design->module(cell->type);
 +		log_assert(orig_box_module);
 +		IdString derived_name = orig_box_module->derive(design, cell->parameters);
 +		RTLIL::Module* box_module = design->module(derived_name);
- 		if (box_module->has_processes())
- 			Pass::call_on_module(design, box_module, "proc");
- 
- 		int box_inputs = 0;
- 		auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
- 		Cell *holes_cell = r.first->second;
- 		if (r.second && box_module->get_bool_attribute("\\whitebox")) {
- 			holes_cell = holes_module->addCell(cell->name, cell->type);
- 			holes_cell->parameters = cell->parameters;
- 			r.first->second = holes_cell;
- 		}
 +
- 		auto r2 = box_ports.insert(cell->type);
- 		if (r2.second) {
- 			// Make carry in the last PI, and carry out the last PO
- 			//   since ABC requires it this way
- 			IdString carry_in, carry_out;
- 			for (const auto &port_name : box_module->ports) {
- 				auto w = box_module->wire(port_name);
- 				log_assert(w);
- 				if (w->get_bool_attribute("\\abc9_carry")) {
- 					if (w->port_input) {
- 						if (carry_in != IdString())
- 							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
- 						carry_in = port_name;
- 					}
- 					if (w->port_output) {
- 						if (carry_out != IdString())
- 							log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
- 						carry_out = port_name;
++		auto r = cell_cache.insert(derived_name);
++		auto &holes_cell = r.first->second;
++		if (r.second) {
++			if (box_module->has_processes())
++				Pass::call_on_module(design, box_module, "proc");
++
++			auto r2 = box_ports.insert(cell->type);
++			if (r2.second) {
++				// Make carry in the last PI, and carry out the last PO
++				//   since ABC requires it this way
++				IdString carry_in, carry_out;
++				for (const auto &port_name : box_module->ports) {
++					auto w = box_module->wire(port_name);
++					log_assert(w);
++					if (w->get_bool_attribute("\\abc9_carry")) {
++						if (w->port_input) {
++							if (carry_in != IdString())
++								log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
++							carry_in = port_name;
++						}
++						if (w->port_output) {
++							if (carry_out != IdString())
++								log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
++							carry_out = port_name;
++						}
 +					}
++					else
++						r2.first->second.push_back(port_name);
 +				}
- 				else
- 					r2.first->second.push_back(port_name);
- 			}
 +
- 			if (carry_in != IdString() && carry_out == IdString())
- 				log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
- 			if (carry_in == IdString() && carry_out != IdString())
- 				log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
- 			if (carry_in != IdString()) {
- 				r2.first->second.push_back(carry_in);
- 				r2.first->second.push_back(carry_out);
++				if (carry_in != IdString() && carry_out == IdString())
++					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
++				if (carry_in == IdString() && carry_out != IdString())
++					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
++				if (carry_in != IdString()) {
++					r2.first->second.push_back(carry_in);
++					r2.first->second.push_back(carry_out);
++				}
 +			}
- 		}
 +
- 		for (const auto &port_name : box_ports.at(cell->type)) {
- 			RTLIL::Wire *w = box_module->wire(port_name);
- 			log_assert(w);
- 			RTLIL::Wire *holes_wire;
- 			RTLIL::SigSpec port_sig;
- 			if (w->port_input)
- 				for (int i = 0; i < GetSize(w); i++) {
++			if (box_module->get_bool_attribute("\\whitebox")) {
++				holes_cell = holes_module->addCell(cell->name, derived_name);
++
++				int box_inputs = 0;
++				for (auto port_name : box_ports.at(cell->type)) {
++					RTLIL::Wire *w = box_module->wire(port_name);
++					log_assert(w);
++					log_assert(!w->port_input || !w->port_output);
++					auto &conn = holes_cell->connections_[port_name];
++					if (w->port_input) {
++						for (int i = 0; i < GetSize(w); i++) {
++							box_inputs++;
++							RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
++							if (!holes_wire) {
++								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
++								holes_wire->port_input = true;
++								holes_wire->port_id = port_id++;
++								holes_module->ports.push_back(holes_wire->name);
++							}
++							conn.append(holes_wire);
++						}
++					}
++					else if (w->port_output)
++						conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
++				}
++
++				// For flops only, create an extra 1-bit input that drives a new wire
++				//   called "<cell>.abc9_ff.Q" that is used below
++				if (box_module->get_bool_attribute("\\abc9_flop")) {
 +					box_inputs++;
- 					holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
++					Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
 +					if (!holes_wire) {
 +						holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
 +						holes_wire->port_input = true;
 +						holes_wire->port_id = port_id++;
 +						holes_module->ports.push_back(holes_wire->name);
 +					}
- 					if (holes_cell)
- 						port_sig.append(holes_wire);
- 				}
- 			if (w->port_output)
- 				for (int i = 0; i < GetSize(w); i++) {
- 					if (GetSize(w) == 1)
- 						holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
- 					else
- 						holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
- 					holes_wire->port_output = true;
- 					holes_wire->port_id = port_id++;
- 					holes_module->ports.push_back(holes_wire->name);
- 					if (holes_cell)
- 						port_sig.append(holes_wire);
- 					else
- 						holes_module->connect(holes_wire, State::S0);
++					Wire *Q = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
++					holes_module->connect(Q, holes_wire);
 +				}
- 			if (!port_sig.empty()) {
- 				if (r.second)
- 					holes_cell->setPort(w->name, port_sig);
- 				else
- 					holes_module->connect(holes_cell->getPort(w->name), port_sig);
 +			}
++			else // box_module is a blackbox
++				log_assert(holes_cell == nullptr);
 +		}
 +
- 		// For flops only, create an extra 1-bit input that drives a new wire
- 		//   called "<cell>.$abc9_currQ" that is used below
- 		if (box_module->get_bool_attribute("\\abc9_flop")) {
- 			log_assert(holes_cell);
- 
- 			box_inputs++;
- 			Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
- 			if (!holes_wire) {
- 				holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
- 				holes_wire->port_input = true;
- 				holes_wire->port_id = port_id++;
- 				holes_module->ports.push_back(holes_wire->name);
- 			}
- 			Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
- 			holes_module->connect(w, holes_wire);
++		for (auto port_name : box_ports.at(cell->type)) {
++			RTLIL::Wire *w = box_module->wire(port_name);
++			log_assert(w);
++			if (!w->port_output)
++				continue;
++			Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
++			holes_wire->port_output = true;
++			holes_wire->port_id = port_id++;
++			holes_module->ports.push_back(holes_wire->name);
++			if (holes_cell) // whitebox
++				holes_module->connect(holes_wire, holes_cell->getPort(port_name));
++			else // blackbox
++				holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
 +		}
 +	}
 +}
 +
 +void reintegrate(RTLIL::Module *module)
 +{
 +	auto design = module->design;
 +	log_assert(design);
 +
 +	map_autoidx = autoidx++;
 +
 +	RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
 +	if (mapped_mod == NULL)
 +		log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
 +
 +	for (auto w : mapped_mod->wires())
 +		module->addWire(remap_name(w->name), GetSize(w));
 +
 +	dict<IdString,IdString> box_lookup;
 +	dict<IdString,std::vector<IdString>> box_ports;
 +
 +	for (auto m : design->modules()) {
 +		auto it = m->attributes.find(ID(abc9_box_id));
 +		if (it == m->attributes.end())
 +			continue;
 +		if (m->name.begins_with("$paramod"))
 +			continue;
 +		auto id = it->second.as_int();
 +		auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
 +		if (!r.second)
 +			log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
 +					log_id(m), id, log_id(r.first->second));
 +		log_assert(r.second);
 +
 +		auto r2 = box_ports.insert(m->name);
 +		if (r2.second) {
 +			// Make carry in the last PI, and carry out the last PO
 +			//   since ABC requires it this way
 +			IdString carry_in, carry_out;
 +			for (const auto &port_name : m->ports) {
 +				auto w = m->wire(port_name);
 +				log_assert(w);
 +				if (w->get_bool_attribute("\\abc9_carry")) {
 +					if (w->port_input) {
 +						if (carry_in != IdString())
 +							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
 +						carry_in = port_name;
 +					}
 +					if (w->port_output) {
 +						if (carry_out != IdString())
 +							log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
 +						carry_out = port_name;
 +					}
 +				}
 +				else
 +					r2.first->second.push_back(port_name);
 +			}
 +
 +			if (carry_in != IdString() && carry_out == IdString())
 +				log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
 +			if (carry_in == IdString() && carry_out != IdString())
 +				log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
 +			if (carry_in != IdString()) {
 +				r2.first->second.push_back(carry_in);
 +				r2.first->second.push_back(carry_out);
 +			}
 +		}
 +	}
 +
 +	std::vector<Cell*> boxes;
 +	for (auto cell : module->cells().to_vector()) {
 +		if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
 +			module->remove(cell);
 +		else if (cell->attributes.erase("\\abc9_box_seq"))
 +			boxes.emplace_back(cell);
 +	}
 +
 +	dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 +	TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
 +	dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
 +	dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
 +
 +	std::map<IdString, int> cell_stats;
 +	for (auto mapped_cell : mapped_mod->cells())
 +	{
 +		toposort.node(mapped_cell->name);
 +
 +		if (mapped_cell->type == ID($_NOT_)) {
 +			RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
 +			RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
 +			bit_users[a_bit].insert(mapped_cell->name);
 +			bit_drivers[y_bit].insert(mapped_cell->name);
 +
 +			if (!a_bit.wire) {
 +				mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
 +				RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
 +				log_assert(wire);
 +				module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
 +			}
 +			else {
 +				RTLIL::Cell* driver_lut = nullptr;
 +				// ABC can return NOT gates that drive POs
 +				if (!a_bit.wire->port_input) {
 +					// If it's not a NOT gate that that comes from a PI directly,
 +					// find the driver LUT and clone that to guarantee that we won't
 +					// increase the max logic depth
 +					// (TODO: Optimise by not cloning unless will increase depth)
 +					RTLIL::IdString driver_name;
 +					if (GetSize(a_bit.wire) == 1)
 +						driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
 +					else
 +						driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
 +					driver_lut = mapped_mod->cell(driver_name);
 +				}
 +
 +				if (!driver_lut) {
 +					// If a driver couldn't be found (could be from PI or box CI)
 +					// then implement using a LUT
 +					RTLIL::Cell *cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
 +							RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
 +							RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
 +							RTLIL::Const::from_string("01"));
 +					bit2sinks[cell->getPort(ID::A)].push_back(cell);
 +					cell_stats[ID($lut)]++;
 +				}
 +				else
 +					not2drivers[mapped_cell] = driver_lut;
 +			}
 +			continue;
 +		}
 +
 +		if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
 +			// Convert buffer into direct connection
 +			if (mapped_cell->type == ID($lut) &&
 +					GetSize(mapped_cell->getPort(ID::A)) == 1 &&
 +					mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
 +				SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
 +				SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
 +				module->connect(my_y, my_a);
 +				log_abort();
 +				continue;
 +			}
 +			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 +			cell->parameters = mapped_cell->parameters;
 +			cell->attributes = mapped_cell->attributes;
 +
 +			for (auto &mapped_conn : mapped_cell->connections()) {
 +				RTLIL::SigSpec newsig;
 +				for (auto c : mapped_conn.second.chunks()) {
 +					if (c.width == 0)
 +						continue;
 +					//log_assert(c.width == 1);
 +					if (c.wire)
 +						c.wire = module->wires_.at(remap_name(c.wire->name));
 +					newsig.append(c);
 +				}
 +				cell->setPort(mapped_conn.first, newsig);
 +
 +				if (cell->input(mapped_conn.first)) {
 +					for (auto i : newsig)
 +						bit2sinks[i].push_back(cell);
 +					for (auto i : mapped_conn.second)
 +						bit_users[i].insert(mapped_cell->name);
 +				}
 +				if (cell->output(mapped_conn.first))
 +					for (auto i : mapped_conn.second)
 +						bit_drivers[i].insert(mapped_cell->name);
 +			}
 +		}
 +		else {
 +			RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
 +			log_assert(existing_cell);
 +			log_assert(mapped_cell->type.begins_with("$__boxid"));
 +
 +			auto type = box_lookup.at(mapped_cell->type, IdString());
 +			if (type == IdString())
 +				log_error("No module with abc9_box_id = %s found.\n", mapped_cell->type.c_str() + strlen("$__boxid"));
 +			mapped_cell->type = type;
 +
 +			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 +			cell->parameters = existing_cell->parameters;
 +			cell->attributes = existing_cell->attributes;
 +			module->swap_names(cell, existing_cell);
 +
 +			auto it = mapped_cell->connections_.find("\\i");
 +			log_assert(it != mapped_cell->connections_.end());
 +			SigSpec inputs = std::move(it->second);
 +			mapped_cell->connections_.erase(it);
 +			it = mapped_cell->connections_.find("\\o");
 +			log_assert(it != mapped_cell->connections_.end());
 +			SigSpec outputs = std::move(it->second);
 +			mapped_cell->connections_.erase(it);
 +
 +			RTLIL::Module* box_module = design->module(mapped_cell->type);
 +			auto abc9_flop = box_module->attributes.count("\\abc9_flop");
 +			if (!abc9_flop) {
 +				for (const auto &i : inputs)
 +					bit_users[i].insert(mapped_cell->name);
 +				for (const auto &i : outputs)
 +					bit_drivers[i].insert(mapped_cell->name);
 +			}
 +
 +			int input_count = 0, output_count = 0;
 +			for (const auto &port_name : box_ports.at(cell->type)) {
 +				RTLIL::Wire *w = box_module->wire(port_name);
 +				log_assert(w);
 +
 +				SigSpec sig;
 +				if (w->port_input) {
 +					sig = inputs.extract(input_count, GetSize(w));
 +					input_count += GetSize(w);
 +				}
 +				if (w->port_output) {
 +					sig = outputs.extract(output_count, GetSize(w));
 +					output_count += GetSize(w);
 +				}
 +
 +				SigSpec newsig;
 +				for (auto c : sig.chunks()) {
 +					if (c.width == 0)
 +						continue;
 +					//log_assert(c.width == 1);
 +					if (c.wire)
 +						c.wire = module->wires_.at(remap_name(c.wire->name));
 +					newsig.append(c);
 +				}
 +
 +				auto it = existing_cell->connections_.find(port_name);
 +				if (it == existing_cell->connections_.end())
 +					continue;
 +				if (GetSize(newsig) > GetSize(it->second))
 +					newsig = newsig.extract(0, GetSize(it->second));
 +				else
 +					log_assert(GetSize(newsig) == GetSize(it->second));
 +
 +				cell->setPort(port_name, newsig);
 +
 +				if (w->port_input && !abc9_flop)
 +					for (const auto &i : newsig)
 +						bit2sinks[i].push_back(cell);
 +			}
 +		}
 +
 +		cell_stats[mapped_cell->type]++;
 +	}
 +
 +	for (auto cell : boxes)
 +		module->remove(cell);
 +
 +	// Copy connections (and rename) from mapped_mod to module
 +	for (auto conn : mapped_mod->connections()) {
 +		if (!conn.first.is_fully_const()) {
 +			auto chunks = conn.first.chunks();
 +			for (auto &c : chunks)
 +				c.wire = module->wires_.at(remap_name(c.wire->name));
 +			conn.first = std::move(chunks);
 +		}
 +		if (!conn.second.is_fully_const()) {
 +			auto chunks = conn.second.chunks();
 +			for (auto &c : chunks)
 +				if (c.wire)
 +					c.wire = module->wires_.at(remap_name(c.wire->name));
 +			conn.second = std::move(chunks);
 +		}
 +		module->connect(conn);
 +	}
 +
 +	for (auto &it : cell_stats)
 +		log("ABC RESULTS:   %15s cells: %8d\n", it.first.c_str(), it.second);
 +	int in_wires = 0, out_wires = 0;
 +
 +	// Stitch in mapped_mod's inputs/outputs into module
 +	for (auto port : mapped_mod->ports) {
 +		RTLIL::Wire *w = mapped_mod->wire(port);
 +		RTLIL::Wire *wire = module->wire(port);
 +		log_assert(wire);
 +		RTLIL::Wire *remap_wire = module->wire(remap_name(port));
 +		RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
 +		log_assert(GetSize(signal) >= GetSize(remap_wire));
 +
 +		RTLIL::SigSig conn;
 +		if (w->port_output) {
 +			conn.first = signal;
 +			conn.second = remap_wire;
 +			out_wires++;
 +			module->connect(conn);
 +		}
 +		else if (w->port_input) {
 +			conn.first = remap_wire;
 +			conn.second = signal;
 +			in_wires++;
 +			module->connect(conn);
 +		}
 +	}
 +
 +	for (auto &it : bit_users)
 +		if (bit_drivers.count(it.first))
 +			for (auto driver_cell : bit_drivers.at(it.first))
 +			for (auto user_cell : it.second)
 +				toposort.edge(driver_cell, user_cell);
 +	bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
 +	log_assert(no_loops);
 +
 +	for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
 +		RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
 +		log_assert(not_cell);
 +		if (not_cell->type != ID($_NOT_))
 +			continue;
 +		auto it = not2drivers.find(not_cell);
 +		if (it == not2drivers.end())
 +			continue;
 +		RTLIL::Cell *driver_lut = it->second;
 +		RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
 +		RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
 +		RTLIL::Const driver_mask;
 +
 +		a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
 +		y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
 +
 +		auto jt = bit2sinks.find(a_bit);
 +		if (jt == bit2sinks.end())
 +			goto clone_lut;
 +
 +		for (auto sink_cell : jt->second)
 +			if (sink_cell->type != ID($lut))
 +				goto clone_lut;
 +
 +		// Push downstream LUTs past inverter
 +		for (auto sink_cell : jt->second) {
 +			SigSpec A = sink_cell->getPort(ID::A);
 +			RTLIL::Const mask = sink_cell->getParam(ID(LUT));
 +			int index = 0;
 +			for (; index < GetSize(A); index++)
 +				if (A[index] == a_bit)
 +					break;
 +			log_assert(index < GetSize(A));
 +			int i = 0;
 +			while (i < GetSize(mask)) {
 +				for (int j = 0; j < (1 << index); j++)
 +					std::swap(mask[i+j], mask[i+j+(1 << index)]);
 +				i += 1 << (index+1);
 +			}
 +			A[index] = y_bit;
 +			sink_cell->setPort(ID::A, A);
 +			sink_cell->setParam(ID(LUT), mask);
 +		}
 +
 +		// Since we have rewritten all sinks (which we know
 +		// to be only LUTs) to be after the inverter, we can
 +		// go ahead and clone the LUT with the expectation
 +		// that the original driving LUT will become dangling
 +		// and get cleaned away
 +clone_lut:
 +		driver_mask = driver_lut->getParam(ID(LUT));
 +		for (auto &b : driver_mask.bits) {
 +			if (b == RTLIL::State::S0) b = RTLIL::State::S1;
 +			else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
 +		}
 +		auto cell = module->addLut(NEW_ID,
 +				driver_lut->getPort(ID::A),
 +				y_bit,
 +				driver_mask);
 +		for (auto &bit : cell->connections_.at(ID::A)) {
 +			bit.wire = module->wires_.at(remap_name(bit.wire->name));
 +			bit2sinks[bit].push_back(cell);
 +		}
 +	}
 +
 +	//log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
 +	log("ABC RESULTS:           input signals: %8d\n", in_wires);
 +	log("ABC RESULTS:          output signals: %8d\n", out_wires);
 +
 +	design->remove(mapped_mod);
 +}
 +
 +struct Abc9OpsPass : public Pass {
 +	Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
 +	void help() YS_OVERRIDE
 +	{
 +		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 +		log("\n");
 +		log("    abc9_ops [options] [selection]\n");
 +		log("\n");
 +	}
 +	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 +	{
 +		log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
 +
 +		bool break_scc_mode = false;
 +		bool unbreak_scc_mode = false;
 +		bool prep_dff_mode = false;
 +		bool prep_holes_mode = false;
 +		bool reintegrate_mode = false;
 +		bool dff_mode = false;
 +
 +		size_t argidx;
 +		for (argidx = 1; argidx < args.size(); argidx++) {
 +			std::string arg = args[argidx];
 +			if (arg == "-break_scc") {
 +				break_scc_mode = true;
 +				continue;
 +			}
 +			if (arg == "-unbreak_scc") {
 +				unbreak_scc_mode = true;
 +				continue;
 +			}
 +			if (arg == "-prep_dff") {
 +				prep_dff_mode = true;
 +				continue;
 +			}
 +			if (arg == "-prep_holes") {
 +				prep_holes_mode = true;
 +				continue;
 +			}
 +			if (arg == "-reintegrate") {
 +				reintegrate_mode = true;
 +				continue;
 +			}
 +			if (arg == "-dff") {
 +				dff_mode = true;
 +				continue;
 +			}
 +			break;
 +		}
 +		extra_args(args, argidx, design);
 +
 +		if (!(break_scc_mode || unbreak_scc_mode || prep_dff_mode || reintegrate_mode))
 +			log_cmd_error("At least one of -{,un}break_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
 +
 +		if (dff_mode && !prep_holes_mode)
 +			log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
 +
 +		for (auto mod : design->selected_modules()) {
 +			if (mod->get_bool_attribute("\\abc9_holes"))
 +				continue;
 +
 +			if (mod->processes.size() > 0) {
 +				log("Skipping module %s as it contains processes.\n", log_id(mod));
 +				continue;
 +			}
 +
 +			if (!design->selected_whole_module(mod))
 +				log_error("Can't handle partially selected module %s!\n", log_id(mod));
 +
 +			if (break_scc_mode)
 +				break_scc(mod);
 +			if (unbreak_scc_mode)
 +				unbreak_scc(mod);
 +			if (prep_dff_mode)
 +				prep_dff(mod);
 +			if (prep_holes_mode)
 +				prep_holes(mod, dff_mode);
 +			if (reintegrate_mode)
 +				reintegrate(mod);
 +		}
 +	}
 +} Abc9OpsPass;
 +
 +PRIVATE_NAMESPACE_END