From: lkcl <lkcl@web>
Date: Sat, 21 May 2022 13:32:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2150
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79e175eea79e8bf33473942ca652ab252a09a7c3;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 445083ef7..12108c71c 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -101,7 +101,7 @@ OPF ISA WG):
 
 mode is encoded in XO and is 4 bits
 
-    crrweird: RT, BFA, M, mask.mode
+    crrweird: RT,BFA,M,mask,mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
@@ -125,7 +125,7 @@ sequentially into the destination. *Destination elwidth overrides still apply*.
 
 mode is encoded in XO and is 4 bits
 
-    mfcrrweird: RT, BFA, mask.mode
+    mfcrrweird: RT,BFA,mask,mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
@@ -149,7 +149,7 @@ into the destination.  *Destination elwidth overrides still apply*
 
 mode is encoded in XO and is 4 bits
 
-    mtcrrweird: BF, RA, M, mask.mode
+    mtcrrweird: BF,RA,M,mask,mode
 
     n0 = mask[0] & (mode[0] == RA[63])
     n1 = mask[1] & (mode[1] == RA[62])
@@ -166,7 +166,7 @@ Mode capability
 
 **mtcrweird**
 
-    mtcrweird: BF, RA, M, mask.mode
+    mtcrweird: BF,RA,M,mask,mode
 
     reg = (RA|0)
     lsb = reg[63] # MSB0 numbering
@@ -199,7 +199,7 @@ Unlike `mcrf` the bits of the CR Field may not change position:
 the EQ bit from the source may only go into the EQ bit of the
 destination (optionally inverted, set, or cleared).
 
-    mcrfm: BF, BFA, M, mask.mode
+    mcrfm: BF,BFA,M,mask,mode
 
     result = mask & CR{BFA}
     if M:
@@ -207,7 +207,7 @@ destination (optionally inverted, set, or cleared).
     result ^= mode
     CR{BF} = result
 
-Note that when M=1 this operation is a Read-Modify-Write on the CR Field
+When M=1 this operation is a Read-Modify-Write on the CR Field
 BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
 M=1. Correspondingly when M=0 this operation is an overwrite: no read
 of BF is required because the masked-out bits of the BF CR Field are
@@ -225,7 +225,7 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
 
 **crweirder**
 
-    crweirder: BT, BFA, mask.mode
+    crweirder: BT,BFA,mask,mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
@@ -243,9 +243,9 @@ capability (BFT is 5 bits)
 
 **Example Pseudo-ops:**
 
-    mtcri BF, mode    mtcrweird BF, r0, 0, 0b1111.~mode
-    mtcrset BF, mask  mtcrweird BF, r0, 1, mask.0b0000
-    mtcrclr BF, mask  mtcrweird BF, r0, 1, mask.0b1111
+    mtcri BF, mode    mtcrweird BF, r0, 0, 0b1111,~mode
+    mtcrset BF, mask  mtcrweird BF, r0, 1, mask,0b0000
+    mtcrclr BF, mask  mtcrweird BF, r0, 1, mask,0b1111
 
 # Vectorised versions involving GPRs