From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 28 Nov 2012 21:49:22 +0000 (+0100)
Subject: Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify... 
X-Git-Tag: 24jan2021_ls180~3072
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79e5f24a652708b768151845fe63174d6ae975c7;p=litex.git

Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
---

diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py
index 6ca619bb..ac4b2265 100644
--- a/milkymist/asmicon/multiplexer.py
+++ b/milkymist/asmicon/multiplexer.py
@@ -251,9 +251,10 @@ class Multiplexer:
 		)
 		fsm.act(fsm.REFRESH,
 			steerer.sel[0].eq(STEER_REFRESH),
-			self.refresher.ack.eq(1),
 			If(~self.refresher.req, fsm.next_state(fsm.READ))
 		)
+		# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
+		comb.append(self.refresher.ack.eq(fsm._state == fsm.REFRESH))
 		
 		return Fragment(comb, sync) + \
 			choose_cmd.get_fragment() + \