From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 1 Jul 2020 16:14:47 +0000 (+0100)
Subject: add OP_SC
X-Git-Tag: div_pipeline~185
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79f0306d99e93f93bfef8625a43c4c346b753822;p=soc.git

add OP_SC
---

diff --git a/libreriscv b/libreriscv
index 22a93bad..bd0a43e8 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 22a93badbd972f3f6009ff1a2d7be2948dcb45d2
+Subproject commit bd0a43e88d6ee58a5d331d70e182cbadca54d7b8
diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 415d9e06..f179f2ce 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -201,6 +201,7 @@ class InternalOp(Enum):
     OP_RFID = 70
     OP_MFMSR = 71
     OP_MTMSRD = 72
+    OP_SC = 73
 
 
 @unique