From: Megan Wachs <megan@sifive.com>
Date: Fri, 9 Jun 2017 20:53:22 +0000 (-0700)
Subject: peripheral_options: Actually compiles
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79f64de12cac914c0c195dc876f34adcaf15f7d5;p=sifive-blocks.git

peripheral_options: Actually compiles
---

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 3c7a2ec..38fd20a 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -10,6 +10,7 @@ import rocketchip.{
   HasTopLevelNetworksModule
 }
 import uncore.tilelink2.TLFragmenter
+import util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
@@ -25,13 +26,13 @@ trait HasPeripheryGPIO extends HasTopLevelNetworks {
 
 trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
   val outer: HasPeripheryGPIO
-  val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_))))
+  val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
 }
 
 trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
   val outer: HasPeripheryGPIO
   val io: HasPeripheryGPIOBundle
   (io.gpio zip outer.gpio) foreach { case (io, device) =>
-    io.gpio <> device.module.io.port
+    io <> device.module.io.port
   }
 }
diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 2459b75..daa0a9f 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -52,7 +52,7 @@ trait HasPeripherySPIFlash extends HasTopLevelNetworks {
 
 trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
   val outer: HasPeripherySPIFlash 
-  val qspi = HeterogenousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
+  val qspi = HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
 }
 
 trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
@@ -60,7 +60,7 @@ trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
   val io: HasPeripherySPIFlashBundle
 
   (io.qspi zip outer.qspi) foreach { case (io, device) => 
-    io.qspi <> device.module.io.port
+    io <> device.module.io.port
   }
 }