From: Megan Wachs <megan@sifive.com>
Date: Fri, 24 Mar 2017 20:24:45 +0000 (-0700)
Subject: SPI: TEMP HACK  do not merge!
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79fa330cdfa70aa3eb9c5aea4254168736b62061;p=sifive-blocks.git

SPI: TEMP HACK  do not merge!

Hard code 3-cycle synchronizer for SPI input without Pinmux.
---

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 1509ea7..229559e 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -56,4 +56,8 @@ trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
   val outer: HasPeripherySPIFlash
   val io: HasPeripherySPIFlashBundle
   io.qspi <> outer.qspi.module.io.port
+  //HACK -- introduce delay elements to synchronize these inputs.
+  (io.qspi.dq zip outer.qspi.module.io.port.dq).foreach{ case (i, o) => 
+    o.i := ShiftRegister(i.i, 3)
+  }
 }