From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 19:14:37 +0000 (-0700)
Subject: Cleanup, call pmux2shiftx even without -nosrl
X-Git-Tag: working-ls180~1208^2~327
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=79fb291dbedbb6cf582925329e8140cbc7e502a9;p=yosys.git

Cleanup, call pmux2shiftx even without -nosrl
---

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 43be55d51..296edace9 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,9 +30,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
new file mode 100644
index 000000000..d572817df
--- /dev/null
+++ b/techlibs/xilinx/abc.box
@@ -0,0 +1,19 @@
+# Max delays from https://pastebin.com/v2hrcksd
+# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+
+# F7BMUX slower than F7AMUX
+# Inputs: I0 I1 S0
+# Outputs: O
+F7BMUX 1 1 3 1
+217 223 296
+
+# Inputs: I0 I1 S0
+# Outputs: O
+MUXF8 2 1 3 1
+104 94 273
+
+MUXCY 3 1 3 1
+1 1 1
+
+XORCY 4 1 2 1
+1 1
diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
new file mode 100644
index 000000000..c6bc7b1f7
--- /dev/null
+++ b/techlibs/xilinx/abc.lut
@@ -0,0 +1,12 @@
+# Max delays from https://pastebin.com/v2hrcksd
+# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+
+# K	area	delay
+1 	11	624
+2	12	624
+3	13	624
+4	14	624
+5	15	624
+6	20	724
+7	40	1020
+8	80	1293
diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box
deleted file mode 100644
index 5ad284f47..000000000
--- a/techlibs/xilinx/cells.box
+++ /dev/null
@@ -1,19 +0,0 @@
-# Max delays from https://pastebin.com/v2hrcksd
-# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
-
-# F7BMUX slower than F7AMUX
-# Inputs: 0 1 S0
-# Outputs: OUT
-F7BMUX 1 1 3 1
-217 223 296
-
-# Inputs: 0 1 S0
-# Outputs: OUT
-MUXF8 2 1 3 1
-104 94 273
-
-MUXCY 3 1 3 1
-1 1 1
-
-XORCY 4 1 2 1
-1 1
diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut
deleted file mode 100644
index c6bc7b1f7..000000000
--- a/techlibs/xilinx/cells.lut
+++ /dev/null
@@ -1,12 +0,0 @@
-# Max delays from https://pastebin.com/v2hrcksd
-# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
-
-# K	area	delay
-1 	11	624
-2	12	624
-3	13	624
-4	14	624
-5	15	624
-6	20	724
-7	40	1020
-8	80	1293
diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v
deleted file mode 100644
index ef6f81d27..000000000
--- a/techlibs/xilinx/cells_box.v
+++ /dev/null
@@ -1,19 +0,0 @@
-(* abc_box_id = 1 *)
-module MUXF7(output O, input I0, I1, S);
-  assign O = S ? I1 : I0;
-endmodule
-
-(* abc_box_id = 2 *)
-module MUXF8(output O, input I0, I1, S);
-  assign O = S ? I1 : I0;
-endmodule
-
-(* abc_box_id = 3 *)
-module MUXCY(output O, input CI, DI, S);
-  assign O = S ? CI : DI;
-endmodule
-
-(* abc_box_id = 4 *)
-module XORCY(output O, input CI, LI);
-  assign O = CI ^ LI;
-endmodule
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3a4540b83..8b231480f 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -155,18 +155,22 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
   assign O5 = I0 ? s5_1[1] : s5_1[0];
 endmodule
 
+(* abc_box_id = 3, lib_whitebox *)
 module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
+(* abc_box_id = 1, lib_whitebox *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+(* abc_box_id = 2, lib_whitebox *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+(* abc_box_id = 4, lib_whitebox *)
 module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
@@ -202,7 +206,7 @@ endmodule
 
 `endif
 
-module FDRE (output reg Q, input C, CE, D, R);
+module FDRE ((* abc_flop_q *) output reg Q, input C, CE, input D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -214,7 +218,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   endcase endgenerate
 endmodule
 
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -226,7 +230,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   endcase endgenerate
 endmodule
 
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -240,7 +244,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   endcase endgenerate
 endmodule
 
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -254,32 +258,32 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
 module RAM64X1D (
-  output DPO, SPO,
+  (* abc_flop_q *) output DPO, SPO,
   input  D, WCLK, WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@ -296,7 +300,7 @@ module RAM64X1D (
 endmodule
 
 module RAM128X1D (
-  output       DPO, SPO,
+  (* abc_flop_q *) output       DPO, SPO,
   input        D, WCLK, WE,
   input  [6:0] A, DPRA
 );
@@ -310,7 +314,7 @@ module RAM128X1D (
 endmodule
 
 module SRL16E (
-  output Q,
+  (* abc_flop_q *) output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -328,7 +332,7 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  output Q,
+  (* abc_flop_q *) output Q,
   output Q31,
   input [4:0] A,
   input CE, CLK, D
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index fa87a3ad6..5de2803e9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -119,8 +119,8 @@ struct SynthXilinxPass : public Pass
 		log("        opt -fast\n");
 		log("\n");
 		log("    map_cells:\n");
+		log("        pmux2shiftx\n");
 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
-		log("        pmux2shiftx (without '-nosrl' only)\n");
 		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
 		log("        techmap -map +/xilinx/cells_map.v\n");
@@ -288,14 +288,16 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
+			// shregmap -tech xilinx can cope with $shiftx and $mux
+			//   cells for identifying variable-length shift registers,
+			//   so attempt to convert $pmux-es to the former
+			// Also: wide multiplexers inference benefits from this too
+			Pass::call(design, "pmux2shiftx");
+
 			if (!nosrl) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
 				Pass::call(design, "simplemap t:$dff t:$dffe");
-				// shregmap -tech xilinx can cope with $shiftx and $mux
-				//   cells for identifiying variable-length shift registers,
-				//   so attempt to convert $pmux-es to the former
-				Pass::call(design, "pmux2shiftx");
 				// pmux2shiftx can leave behind a $pmux with a single entry
 				//   -- need this to clean that up before shregmap
 				Pass::call(design, "opt_expr -mux_undef");
@@ -311,9 +313,8 @@ struct SynthXilinxPass : public Pass
 		{
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
-			Pass::call(design, "read_verilog +/xilinx/cells_box.v");
 			if (abc == "abc9")
-				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
+				Pass::call(design, abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
 			else
 				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");