From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 12 Mar 2019 06:46:48 +0000 (+0000)
Subject: remove whitespace
X-Git-Tag: div_pipeline~2305
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a02d543b71ac349f3f8a8ce99606744f142b836;p=soc.git

remove whitespace
---

diff --git a/TLB/src/Cam.py b/TLB/src/Cam.py
index ab8f2c15..1cb88d88 100644
--- a/TLB/src/Cam.py
+++ b/TLB/src/Cam.py
@@ -24,9 +24,9 @@ class Cam():
         Notes:
         The read and write operations take one clock cycle to complete.
         Currently the read_warning line is present for interfacing but
-        is not necessary for this design. This module is capable of writing 
+        is not necessary for this design. This module is capable of writing
         in the first cycle, reading on the second, and output the correct
-        address on the third. 
+        address on the third.
     """
 
     def __init__(self, data_size, cam_size):