From: Alan Modra Date: Tue, 26 Mar 2019 05:16:14 +0000 (+1030) Subject: [RS6000] Fix typos X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a03cad76c1d2d7f156424f0bd9290dfcb1d4488;p=gcc.git [RS6000] Fix typos * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Correct rs6000_vector_mem init. Correct wI and wJ comment From-SVN: r269932 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 457b598f1e5..4af4550c824 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-03-26 Alan Modra + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Correct + rs6000_vector_mem init. Correct wI and wJ comment. + 2019-03-25 Alexander Monakov PR rtl-optimization/88347 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 06ce2892bf9..a7590db013e 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3050,7 +3050,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) below. */ gcc_assert ((int)VECTOR_NONE == 0); memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit)); - memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit)); + memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_mem)); gcc_assert ((int)CODE_FOR_nothing == 0); memset ((void *) ®_addr[0], '\0', sizeof (reg_addr)); @@ -3204,8 +3204,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wy - Register class to do ISA 2.07 SF operations. wz - Float register if we can do 32-bit unsigned int loads. wH - Altivec register if SImode is allowed in VSX registers. - wI - VSX register if SImode is allowed in VSX registers. - wJ - VSX register if QImode/HImode are allowed in VSX registers. + wI - Float register if SImode is allowed in VSX registers. + wJ - Float register if QImode/HImode are allowed in VSX registers. wK - Altivec register if QImode/HImode are allowed in VSX registers. */ if (TARGET_HARD_FLOAT)