From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 18 Jun 2019 09:03:52 +0000 (+0100)
Subject: clarify comment
X-Git-Tag: div_pipeline~1842
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a04c23586a308b253204d4203ad5cecdba3bc34;p=soc.git

clarify comment
---

diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py
index e2fccf87..5754da5b 100644
--- a/src/experiment/compldst.py
+++ b/src/experiment/compldst.py
@@ -214,7 +214,7 @@ class LDSTCompUnit(Elaboratable):
             with m.If(~self.alu.p_ready_o):          # no ACK yet
                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 
-        # put the register directly onto the output
+        # put the register directly onto the output bus
         with m.If((self.go_wr_i & ~op_ldst) | (self.go_st_i & op_is_st)):
             comb += self.data_o.eq(data_r)