From: Mateusz Holenko <mholenko@antmicro.com>
Date: Thu, 23 Jan 2020 12:37:02 +0000 (+0100)
Subject: soc_core: rename integrated_sram_size argument
X-Git-Tag: 24jan2021_ls180~719^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a05353aa7949707f23453b6db013e2a62ecc8d9;p=litex.git

soc_core: rename integrated_sram_size argument

To keep a consistent naming scheme across all arguments.
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index b8ee639d..6f61a213 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -612,7 +612,7 @@ def soc_core_args(parser):
     parser.add_argument("--integrated-rom-file", default=None, type=str,
                         help="integrated (BIOS) ROM binary file (default=32KB)")
     # SRAM parameters
-    parser.add_argument("--integrated_sram_size", default=0x1000, type=int,
+    parser.add_argument("--integrated-sram-size", default=0x1000, type=int,
                         help="size/enable the integrated SRAM (default=4KB)")
     # MAIN_RAM parameters
     parser.add_argument("--integrated-main-ram-size", default=None, type=int,