From: Ian Romanick Date: Mon, 20 Jan 2014 19:16:26 +0000 (-0800) Subject: radeon / r200: Eliminate BEGIN_BATCH_NO_AUTOSTATE X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a0f26dec9aad75834d3314d5e306d49729b37f1;p=mesa.git radeon / r200: Eliminate BEGIN_BATCH_NO_AUTOSTATE Sed job: grep -lr BEGIN_BATCH_NO_AUTOSTATE src/mesa/drivers/dri/ | while read f do cat $f | sed 's/BEGIN_BATCH_NO_AUTOSTATE/BEGIN_BATCH/g' > x mv x $f done Signed-off-by: Ian Romanick Reviewed-by: Alex Deucher Cc: Marek Olšák --- diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c index a6a1a3fa65c..666fbadc9f8 100644 --- a/src/mesa/drivers/dri/r200/r200_blit.c +++ b/src/mesa/drivers/dri/r200/r200_blit.c @@ -337,7 +337,7 @@ static inline void emit_cb_setup(struct r200_context *r200, if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) dst_pitch |= R200_COLOR_MICROTILE_ENABLE; - BEGIN_BATCH_NO_AUTOSTATE(22); + BEGIN_BATCH(22); OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0); OUT_BATCH_REGVAL(R200_RE_CNTL, 0); OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index b351c20d25c..1e6c0d82484 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -211,7 +211,7 @@ void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count) { BATCH_LOCALS(&rmesa->radeon); - BEGIN_BATCH_NO_AUTOSTATE(2); + BEGIN_BATCH(2); OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0)); OUT_BATCH(count); END_BATCH(); diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 5427fc2059d..a7021f2b6e3 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -169,7 +169,7 @@ static void r200_emit_query_finish(radeonContextPtr radeon) BATCH_LOCALS(radeon); struct radeon_query_object *query = radeon->query.current; - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH(4); OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); END_BATCH(); diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index bf9cef059d1..79aa753dc94 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -293,7 +293,7 @@ VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameter _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ _sz = h.veclinear.count * 4; \ if (_sz) { \ - BEGIN_BATCH_NO_AUTOSTATE(dwords); \ + BEGIN_BATCH(dwords); \ OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ OUT_BATCH(0); \ OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ @@ -346,7 +346,7 @@ static void mtl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1)); OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); END_BATCH(); @@ -358,7 +358,7 @@ static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); END_BATCH(); @@ -370,7 +370,7 @@ static void ptp_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1); OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1); END_BATCH(); @@ -391,7 +391,7 @@ static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_SCL(atom->cmd[0], atom->cmd+1); END_BATCH(); } @@ -403,7 +403,7 @@ static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r200->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[0], atom->cmd+1); END_BATCH(); } @@ -484,7 +484,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) } /* output the first 7 bytes of context */ - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); /* In the CS case we need to split this up */ OUT_BATCH(CP_PACKET0(packet[0].start, 3)); @@ -569,7 +569,7 @@ static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom) if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size)) dwords -= 4; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7)); OUT_BATCH_TABLE((atom->cmd + 1), 8); @@ -599,7 +599,7 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) if (!(t && !t->image_override)) dwords = 2; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH_TABLE(atom->cmd, 2); if (t && !t->image_override) { diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c index 2d4a2d67be4..22a5e036ac6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_blit.c +++ b/src/mesa/drivers/dri/radeon/radeon_blit.c @@ -214,7 +214,7 @@ static inline void emit_cb_setup(struct r100_context *r100, if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) dst_pitch |= RADEON_COLOR_MICROTILE_ENABLE; - BEGIN_BATCH_NO_AUTOSTATE(18); + BEGIN_BATCH(18); OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) | ((height - 1) << RADEON_RE_HEIGHT_SHIFT))); diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h index 63f51c35772..31b95fd661a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h @@ -28,16 +28,11 @@ void rcommonBeginBatch(radeonContextPtr rmesa, const radeonContextPtr b_l_rmesa = rmesa /** - * Prepare writing n dwords to the command buffer, - * including producing any necessary state emits on buffer wraparound. + * Prepare writing n dwords to the command buffer. Does not cause automatic + * state emits. */ #define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __FUNCTION__, __LINE__) -/** - * Same as BEGIN_BATCH, but do not cause automatic state emits. - */ -#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __FUNCTION__, __LINE__) - /** * Write one dword to the command buffer. */ diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 4078fdfe14b..67c6dc7b2a7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -499,7 +499,7 @@ static INLINE void radeon_emit_atom(radeonContextPtr radeon, struct radeon_state if (atom->emit) { (*atom->emit)(&radeon->glCtx, atom); } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); END_BATCH(); } diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 0757f7ec4ad..73fd1880f1c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -135,7 +135,7 @@ static void r100_emit_query_finish(radeonContextPtr radeon) BATCH_LOCALS(radeon); struct radeon_query_object *query = radeon->query.current; - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH(4); OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); END_BATCH(); diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index d28a503d94d..fdb1a57701d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -234,7 +234,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, align_min_nr = (min_nr + 1) & ~1; #if RADEON_OLD_PACKETS - BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4); + BEGIN_BATCH(2+ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0); OUT_BATCH(rmesa->ioctl.vertex_offset); OUT_BATCH(rmesa->ioctl.vertex_max); @@ -244,7 +244,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); #else - BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4); + BEGIN_BATCH(ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); OUT_BATCH(vertex_format); OUT_BATCH(primitive | diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c index 705d612e10b..7efe52f0ef0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c +++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c @@ -209,7 +209,7 @@ void radeon_emit_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom dwords = (*atom->check) (ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); END_BATCH(); diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index e3bd6a09411..ee8880027d4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -263,7 +263,7 @@ static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_SCL(atom->cmd[0], atom->cmd+1); END_BATCH(); } @@ -275,7 +275,7 @@ static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[0], atom->cmd+1); END_BATCH(); } @@ -287,7 +287,7 @@ static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); END_BATCH(); @@ -366,7 +366,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) } - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); /* In the CS case we need to split this up */ OUT_BATCH(CP_PACKET0(packet[0].start, 3)); @@ -399,7 +399,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) // } END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH(4); OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); OUT_BATCH(0); OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); @@ -437,7 +437,7 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) default: case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; }; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH_TABLE(atom->cmd, 2); lvl = &t->mt->levels[0]; for (j = 0; j < 5; j++) { @@ -469,7 +469,7 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) dwords += 2; else dwords -= 2; - BEGIN_BATCH_NO_AUTOSTATE(dwords); + BEGIN_BATCH(dwords); OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); OUT_BATCH_TABLE((atom->cmd + 1), 2);