From: Jacob Lifshay Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700) Subject: split out instructions from openpower/isa/pifixedload.mdwn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a3046f06d9218ec1300058f360daec324828b32;p=openpower-isa.git split out instructions from openpower/isa/pifixedload.mdwn --- diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn index b5671cbc..5fb7c22c 100644 --- a/openpower/isa/pifixedload.mdwn +++ b/openpower/isa/pifixedload.mdwn @@ -8,179 +8,24 @@ -# Load Byte and Zero with Post-Update +[[!inline pagenames="openpower/isa/pifixedload/lbzup" raw="yes"]] -D-Form +[[!inline pagenames="openpower/isa/pifixedload/lbzupx" raw="yes"]] -* lbzup RT,D(RA) +[[!inline pagenames="openpower/isa/pifixedload/lhzup" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/pifixedload/lhzupx" raw="yes"]] - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + EXTS(D) +[[!inline pagenames="openpower/isa/pifixedload/lhaup" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/pifixedload/lhaupx" raw="yes"]] - None +[[!inline pagenames="openpower/isa/pifixedload/lwzup" raw="yes"]] -# Load Byte and Zero with Post-Update Indexed +[[!inline pagenames="openpower/isa/pifixedload/lwzupx" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/pifixedload/lwaupx" raw="yes"]] -* lbzupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -# Load Halfword and Zero with Post-Update - -D-Form - -* lhzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + EXTS(D) - -Special Registers Altered: - - None - -# Load Halfword and Zero with Post-Update Indexed - -X-Form - -* lhzupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -# Load Halfword Algebraic with Post-Update - -D-Form - -* lhaup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + EXTS(D) - -Special Registers Altered: - - None - -# Load Halfword Algebraic with Post-Update Indexed - -X-Form - -* lhaupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -# Load Word and Zero with Post-Update - -D-Form - -* lwzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- [0]*32 || MEM(EA, 4) - RA <- (RA) + EXTS(D) - -Special Registers Altered: - - None - -# Load Word and Zero with Post-Update Indexed - -X-Form - -* lwzupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- [0] * 32 || MEM(EA, 4) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -# Load Word Algebraic with Post-Update Indexed - -X-Form - -* lwaupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- EXTS(MEM(EA, 4)) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -# Load Doubleword with Post-Update Indexed - -DS-Form - -* ldup RT,DS(RA) - -Pseudo-code: - - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + EXTS(DS || 0b00) - -Special Registers Altered: - - None - -# Load Doubleword with Post-Update Indexed - -X-Form - -* ldupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + (RB) - -Special Registers Altered: - - None +[[!inline pagenames="openpower/isa/pifixedload/ldup" raw="yes"]] +[[!inline pagenames="openpower/isa/pifixedload/ldupx" raw="yes"]] diff --git a/openpower/isa/pifixedload/lbzup.mdwn b/openpower/isa/pifixedload/lbzup.mdwn new file mode 100644 index 00000000..d7863d00 --- /dev/null +++ b/openpower/isa/pifixedload/lbzup.mdwn @@ -0,0 +1,13 @@ +# Load Byte and Zero with Post-Update + +D-Form + +* lbzup RT,D(RA) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lbzup_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lbzup_code.mdwn b/openpower/isa/pifixedload/lbzup_code.mdwn new file mode 100644 index 00000000..12e9895d --- /dev/null +++ b/openpower/isa/pifixedload/lbzup_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- ([0] * (XLEN-8)) || MEM(EA, 1) + RA <- (RA) + EXTS(D) diff --git a/openpower/isa/pifixedload/lbzupx.mdwn b/openpower/isa/pifixedload/lbzupx.mdwn new file mode 100644 index 00000000..8c0d9231 --- /dev/null +++ b/openpower/isa/pifixedload/lbzupx.mdwn @@ -0,0 +1,13 @@ +# Load Byte and Zero with Post-Update Indexed + +X-Form + +* lbzupx RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lbzupx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lbzupx_code.mdwn b/openpower/isa/pifixedload/lbzupx_code.mdwn new file mode 100644 index 00000000..71043bf1 --- /dev/null +++ b/openpower/isa/pifixedload/lbzupx_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- ([0] * (XLEN-8)) || MEM(EA, 1) + RA <- (RA) + (RB) diff --git a/openpower/isa/pifixedload/ldup.mdwn b/openpower/isa/pifixedload/ldup.mdwn new file mode 100644 index 00000000..a61bc1d5 --- /dev/null +++ b/openpower/isa/pifixedload/ldup.mdwn @@ -0,0 +1,13 @@ +# Load Doubleword with Post-Update Indexed + +DS-Form + +* ldup RT,DS(RA) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/ldup_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/ldup_code.mdwn b/openpower/isa/pifixedload/ldup_code.mdwn new file mode 100644 index 00000000..b504e28c --- /dev/null +++ b/openpower/isa/pifixedload/ldup_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- MEM(EA, 8) + RA <- (RA) + EXTS(DS || 0b00) diff --git a/openpower/isa/pifixedload/ldupx.mdwn b/openpower/isa/pifixedload/ldupx.mdwn new file mode 100644 index 00000000..31f0dfff --- /dev/null +++ b/openpower/isa/pifixedload/ldupx.mdwn @@ -0,0 +1,14 @@ +# Load Doubleword with Post-Update Indexed + +X-Form + +* ldupx RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/ldupx_code" raw="yes"]] + +Special Registers Altered: + + None + diff --git a/openpower/isa/pifixedload/ldupx_code.mdwn b/openpower/isa/pifixedload/ldupx_code.mdwn new file mode 100644 index 00000000..0dd78359 --- /dev/null +++ b/openpower/isa/pifixedload/ldupx_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- MEM(EA, 8) + RA <- (RA) + (RB) diff --git a/openpower/isa/pifixedload/lhaup.mdwn b/openpower/isa/pifixedload/lhaup.mdwn new file mode 100644 index 00000000..f79430ee --- /dev/null +++ b/openpower/isa/pifixedload/lhaup.mdwn @@ -0,0 +1,13 @@ +# Load Halfword Algebraic with Post-Update + +D-Form + +* lhaup RT,D(RA) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lhaup_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lhaup_code.mdwn b/openpower/isa/pifixedload/lhaup_code.mdwn new file mode 100644 index 00000000..74a6ef7e --- /dev/null +++ b/openpower/isa/pifixedload/lhaup_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- EXTS(MEM(EA, 2)) + RA <- (RA) + EXTS(D) diff --git a/openpower/isa/pifixedload/lhaupx.mdwn b/openpower/isa/pifixedload/lhaupx.mdwn new file mode 100644 index 00000000..7da0d530 --- /dev/null +++ b/openpower/isa/pifixedload/lhaupx.mdwn @@ -0,0 +1,13 @@ +# Load Halfword Algebraic with Post-Update Indexed + +X-Form + +* lhaupx RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lhaupx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lhaupx_code.mdwn b/openpower/isa/pifixedload/lhaupx_code.mdwn new file mode 100644 index 00000000..3d74c6a4 --- /dev/null +++ b/openpower/isa/pifixedload/lhaupx_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- EXTS(MEM(EA, 2)) + RA <- (RA) + (RB) diff --git a/openpower/isa/pifixedload/lhzup.mdwn b/openpower/isa/pifixedload/lhzup.mdwn new file mode 100644 index 00000000..a482c624 --- /dev/null +++ b/openpower/isa/pifixedload/lhzup.mdwn @@ -0,0 +1,13 @@ +# Load Halfword and Zero with Post-Update + +D-Form + +* lhzup RT,D(RA) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lhzup_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lhzup_code.mdwn b/openpower/isa/pifixedload/lhzup_code.mdwn new file mode 100644 index 00000000..dcf1d5a4 --- /dev/null +++ b/openpower/isa/pifixedload/lhzup_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- ([0] * (XLEN-16)) || MEM(EA, 2) + RA <- (RA) + EXTS(D) diff --git a/openpower/isa/pifixedload/lhzupx.mdwn b/openpower/isa/pifixedload/lhzupx.mdwn new file mode 100644 index 00000000..766cac45 --- /dev/null +++ b/openpower/isa/pifixedload/lhzupx.mdwn @@ -0,0 +1,13 @@ +# Load Halfword and Zero with Post-Update Indexed + +X-Form + +* lhzupx RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lhzupx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lhzupx_code.mdwn b/openpower/isa/pifixedload/lhzupx_code.mdwn new file mode 100644 index 00000000..3303eb91 --- /dev/null +++ b/openpower/isa/pifixedload/lhzupx_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- ([0] * (XLEN-16)) || MEM(EA, 2) + RA <- (RA) + (RB) diff --git a/openpower/isa/pifixedload/lwaupx.mdwn b/openpower/isa/pifixedload/lwaupx.mdwn new file mode 100644 index 00000000..2b90da27 --- /dev/null +++ b/openpower/isa/pifixedload/lwaupx.mdwn @@ -0,0 +1,13 @@ +# Load Word Algebraic with Post-Update Indexed + +X-Form + +* lwaupx RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lwaupx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lwaupx_code.mdwn b/openpower/isa/pifixedload/lwaupx_code.mdwn new file mode 100644 index 00000000..873f1cb8 --- /dev/null +++ b/openpower/isa/pifixedload/lwaupx_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- EXTS(MEM(EA, 4)) + RA <- (RA) + (RB) diff --git a/openpower/isa/pifixedload/lwzup.mdwn b/openpower/isa/pifixedload/lwzup.mdwn new file mode 100644 index 00000000..590d3b3e --- /dev/null +++ b/openpower/isa/pifixedload/lwzup.mdwn @@ -0,0 +1,13 @@ +# Load Word and Zero with Post-Update + +D-Form + +* lwzup RT,D(RA) + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lwzup_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lwzup_code.mdwn b/openpower/isa/pifixedload/lwzup_code.mdwn new file mode 100644 index 00000000..548449cf --- /dev/null +++ b/openpower/isa/pifixedload/lwzup_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- [0]*32 || MEM(EA, 4) + RA <- (RA) + EXTS(D) diff --git a/openpower/isa/pifixedload/lwzupx.mdwn b/openpower/isa/pifixedload/lwzupx.mdwn new file mode 100644 index 00000000..aa30eb64 --- /dev/null +++ b/openpower/isa/pifixedload/lwzupx.mdwn @@ -0,0 +1,13 @@ +# Load Word and Zero with Post-Update Indexed + +X-Form + +* lwzupx RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/pifixedload/lwzupx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/pifixedload/lwzupx_code.mdwn b/openpower/isa/pifixedload/lwzupx_code.mdwn new file mode 100644 index 00000000..e48764f9 --- /dev/null +++ b/openpower/isa/pifixedload/lwzupx_code.mdwn @@ -0,0 +1,3 @@ + EA <- (RA) + RT <- [0] * 32 || MEM(EA, 4) + RA <- (RA) + (RB)