From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Mar 2022 22:52:30 +0000 (-0800)
Subject: add il generation by default
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a3ab7ecce390b2003ff61befca59cd4ad6b7428;p=nmutil.git

add il generation by default
---

diff --git a/src/nmutil/grev.py b/src/nmutil/grev.py
index 35b4565..2b22fe1 100644
--- a/src/nmutil/grev.py
+++ b/src/nmutil/grev.py
@@ -83,6 +83,7 @@ from nmigen.hdl.ast import Signal, Mux, Cat
 from nmigen.hdl.ast import Assert
 from nmigen.hdl.dsl import Module
 from nmigen.hdl.ir import Elaboratable
+from nmigen.back import rtlil
 import string
 
 
@@ -261,3 +262,9 @@ class GRev(Elaboratable):
 # useful to see what is going on:
 # python3 src/nmutil/test/test_grev.py
 # yosys <<<"read_ilang sim_test_out/__main__.TestGrev.test_small/0.il; proc; clean -purge; show top"
+
+if __name__ == '__main__':
+    dut = GRev(3)
+    vl = rtlil.convert(dut, ports=dut.ports())
+    with open("grev3.il", "w") as f:
+        f.write(vl)