From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 16:10:01 +0000 (-0700)
Subject: Missing close bracket
X-Git-Tag: working-ls180~881^2^2~318
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a3c403ba0e411c990be59da44e1decb6aafc8f8;p=yosys.git

Missing close bracket
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 281e1cc9d..d0d2ffdba 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1025,7 +1025,7 @@ struct AigerFrontend : public Frontend {
 		log("        Name of module to be created (default: <filename>)\n");
 		log("\n");
 		log("    -clk_name <wire_name>\n");
-		log("        If specified, AIGER latches to be transformed into $_DFF_P_ cells\n"
+		log("        If specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
 		log("        clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n");
 		log("\n");
 		log("    -map <filename>\n");