From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Jan 2024 14:58:46 +0000 (+0000)
Subject: bug 1034: add crbinlog unit test, fix binlog test, move maddsub*
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a3fb5c8a3;p=openpower-isa.git

bug 1034: add crbinlog unit test, fix binlog test, move maddsub*
---

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index c1275076..3f058868 100644
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -40,9 +40,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 ------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bmask,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----00011-,ALU,OP_FMVIS,NONE,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvis,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----01011-,ALU,OP_FISHMV,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fishmv,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-------01000,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-------01001,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-------01011,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 0101110110-,ALU,OP_BMAT,RA,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,gbbd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 ------00001,SHIFT_ROT,OP_BINLOG,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,binlog,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----001001,CR,OP_CRBINLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crbinlog,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv
index bcc96fd2..80f575ed 100644
--- a/openpower/isatables/minor_5.csv
+++ b/openpower/isatables/minor_5.csv
@@ -1,3 +1,7 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
 --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 --------01-,CR,OP_CRTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------00100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------01100,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------10100,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+
diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py
index 1daaf1df..a84bd2fb 100644
--- a/src/openpower/test/bitmanip/bitmanip_cases.py
+++ b/src/openpower/test/bitmanip/bitmanip_cases.py
@@ -80,6 +80,52 @@ class BitManipTestCase(TestAccumulatorBase):
             msk = hash_256(f"crternlogi msk {i}") % 2 ** 4
             self.do_case_crternlogi(bf, bfa, bfb, imm, msk)
 
+    def do_case_crbinlog(self, bf, bfa, bfb, mask):
+        lst = ["crbinlog 3,4,5,%d" % mask]
+        # set up CR
+        bf %= 2 ** 4
+        bfa %= 2 ** 4
+        bfb %= 2 ** 4
+        cr = CRFields()
+        cr.crl[3][0:4] = bf
+        cr.crl[4][0:4]  = bfa
+        cr.crl[5][0:4]  = bfb
+        lut = bfb
+        initial_cr = cr.cr.asint()
+        print("initial cr", bin(initial_cr), bf, bfa, bfb)
+        print("mask lut2", bin(mask), bin(lut))
+
+        lst = list(SVP64Asm(lst, bigendian))
+        e = ExpectedState(pc=4)
+        expected = bf&~mask # start at BF, mask overwrites masked bits only
+        checks = (bfa, bf) # LUT positions 1<<0=bfa 1<<1=bf
+        for i in range(4):
+            lut_index = 0
+            for j, check in enumerate(checks):
+                if check & (1<<i):
+                    lut_index |= 1<<j
+            maskbit = (mask >> i) & 0b1
+            if (lut & (1<<lut_index)) and maskbit:
+                expected |= 1<<i
+        e.crregs[3] = expected
+        e.crregs[4] = bfa
+        e.crregs[5] = bfb
+        self.add_case(Program(lst, bigendian), initial_regs=None, expected=e,
+                                       initial_cr=initial_cr)
+
+    def case_crbinlog_0(self):
+        self.do_case_crbinlog(0b1111,
+                              0b1100,
+                              0x8, 0b1111)
+
+    def case_crbinlog_random(self):
+        for i in range(100):
+            bf = hash_256(f"crbinlog bf {i}") % 2 ** 4
+            bfa = hash_256(f"crbinlog bfa {i}") % 2 ** 4
+            bfb = hash_256(f"crbinlog bfb {i}") % 2 ** 4
+            msk = hash_256(f"crbinlog msk {i}") % 2 ** 4
+            self.do_case_crbinlog(bf, bfa, bfb, msk)
+
     def do_case_ternlogi(self, rc, rt, ra, rb, imm):
         rc_dot = "." if rc else ""
         lst = [f"ternlogi{rc_dot} 3, 4, 5, {imm}"]
@@ -145,10 +191,10 @@ class BitManipTestCase(TestAccumulatorBase):
     def case_binlog_0(self):
         self.do_case_binlog(0x8000_0000_FFFF_0000,
                             0x8000_0000_FF00_FF00,
-                            0x80, 1)
+                            0x8, 1)
         self.do_case_binlog(0x8000_0000_FFFF_0000,
                             0x8000_0000_FF00_FF00,
-                            0x80, 0)
+                            0x8, 0)
 
     def case_binlog_random(self):
         for i in range(100):