From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 Dec 2021 20:45:04 +0000 (+0000)
Subject: delay MMU LOOKUP done by one clock so that the exception matches timing
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a47d44a1974b9c06c4acfe8e5c01987425d8842;p=soc.git

delay MMU LOOKUP done by one clock so that the exception matches timing
---

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 3f20d9ab..5d0cc814 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -224,7 +224,10 @@ class FSMMMUStage(ControlBase):
                     comb += valid.eq(1)   # start "pulse"
                     comb += ldst.instr_fault.eq(blip)
                     comb += ldst.maddr.eq(nia_i)
-                    comb += done.eq(mmu.d_in.done) # XXX should not access this!
+                    # XXX should not access this!
+                    mmu_done_delay = Signal()
+                    sync += mmu_done_delay.eq(mmu.d_in.done)
+                    comb += done.eq(mmu_done_delay)
                     comb += self.debug0.eq(3)
                     # LDST unit contains exception data, which (messily)
                     # is copied over, here.  not ideal but it will do for now