From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 17 Jun 2016 18:15:11 +0000 (+0200)
Subject: Fixed init issue in mem2reg_test2 test case
X-Git-Tag: yosys-0.7~197
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a4ee5da747382df323d41f60e974ef92bdc1e82;p=yosys.git

Fixed init issue in mem2reg_test2 test case
---

diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 40f490b75..b1ab04d62 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -19,9 +19,9 @@ endmodule
 
 // ------------------------------------------------------
 
-module mem2reg_test2(clk, mode, addr, data);
+module mem2reg_test2(clk, reset, mode, addr, data);
 
-input clk, mode;
+input clk, reset, mode;
 input [2:0] addr;
 output [3:0] data;
 
@@ -33,6 +33,10 @@ assign data = mem[addr];
 integer i;
 
 always @(posedge clk) begin
+	if (reset) begin
+		for (i=0; i<8; i=i+1)
+			mem[i] <= i;
+	end else
 	if (mode) begin
 		for (i=0; i<8; i=i+1)
 			mem[i] <= mem[i]+1;