From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Mon, 16 May 2011 08:38:41 +0000 (-0700)
Subject: [sim,xcc] change cond. mov inst format, add implementation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a589027a771e00646c36bc09dde723c527a26bd;p=riscv-isa-sim.git

[sim,xcc] change cond. mov inst format, add implementation
---

diff --git a/riscv/insns/fmovn.h b/riscv/insns/fmovn.h
index e69de29..394b56c 100644
--- a/riscv/insns/fmovn.h
+++ b/riscv/insns/fmovn.h
@@ -0,0 +1,2 @@
+require_vector;
+if (RS1 & 0x1) FRD = FRS2;
diff --git a/riscv/insns/fmovz.h b/riscv/insns/fmovz.h
index e69de29..7862216 100644
--- a/riscv/insns/fmovz.h
+++ b/riscv/insns/fmovz.h
@@ -0,0 +1,2 @@
+require_vector;
+if (~RS1 & 0x1) FRD = FRS2;
diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h
index e69de29..402d6d3 100644
--- a/riscv/insns/movn.h
+++ b/riscv/insns/movn.h
@@ -0,0 +1,2 @@
+require_vector;
+if (RS1 & 0x1) RD = RS2;
diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h
index e69de29..74cf8a9 100644
--- a/riscv/insns/movz.h
+++ b/riscv/insns/movz.h
@@ -0,0 +1,2 @@
+require_vector;
+if (~RS1 & 0x1) RD = RS2;