From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 May 2023 15:41:21 +0000 (+0100)
Subject: sorted SVP64RMModeDecode to properly match the new spec
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a648ce60ddb7da0062fae7659206dd3613912a1;p=openpower-isa.git

sorted SVP64RMModeDecode to properly match the new spec
---

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index cfc72c28..1f548830 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -203,18 +203,18 @@ class SVP64RMModeDecode(Elaboratable):
         #####################
         with m.Elif(is_cr):
             with m.Switch(mode2):
-                with m.Case(0, 1): # needs further decoding (LDST no mapreduce)
+                with m.Case(0, 2): # needs further decoding (LDST no mapreduce)
                     with m.If(mode[SVP64MODE.REDUCE]):
                         comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
                     with m.Else():
                         comb += self.mode.eq(SVP64RMMode.NORMAL)
-                with m.Case(2,3):
+                with m.Case(1,3):
                     comb += self.mode.eq(SVP64RMMode.FFIRST) # fail-first
 
             # extract failfirst
             with m.If(self.mode == SVP64RMMode.FFIRST): # fail-first
                 comb += self.inv.eq(mode[SVP64MODE.INV])
-                comb += self.vli.eq(mode[SVP64MODE.BC_VLSET])
+                comb += self.vli.eq(mode[SVP64MODE.VLI])
                 with m.If(self.cr_5bit_in):
                     comb += self.cr_sel.eq(0b10) # EQ bit index is implicit
                 with m.Else():