From: Claire Wolf <claire@symbioticeda.com>
Date: Wed, 15 Jul 2020 09:54:28 +0000 (+0200)
Subject: Use %precedence in verilog_parser.y
X-Git-Tag: working-ls180~380^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a79843cc394f59bdd40473a823c7f60c87d3fa6;p=yosys.git

Use %precedence in verilog_parser.y

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 390ef07e9..63f0341d9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -299,14 +299,14 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
 %left '+' '-'
 %left '*' '/' '%'
 %left OP_POW
-%left OP_CAST
-%right UNARY_OPS
+%precedence OP_CAST
+%precedence UNARY_OPS
 
 %define parse.error verbose
 %define parse.lac full
 
-%nonassoc FAKE_THEN
-%nonassoc TOK_ELSE
+%precedence FAKE_THEN
+%precedence TOK_ELSE
 
 %debug
 %locations