From: Xiretza <xiretza@xiretza.xyz>
Date: Mon, 24 Feb 2020 13:39:44 +0000 (+0100)
Subject: Fix ECP5PLL VCO frequency range
X-Git-Tag: 24jan2021_ls180~637^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a87d4e262436b9f693a5a1fce29c36f7247b8d9;p=litex.git

Fix ECP5PLL VCO frequency range

See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index cab8bfce..63a9edaa 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -507,7 +507,7 @@ class ECP5PLL(Module):
     clko_div_range  = (1, 128+1)
     clki_freq_range = (    8e6,  400e6)
     clko_freq_range = (3.125e6,  400e6)
-    vco_freq_range  = (  550e6, 1250e6)
+    vco_freq_range  = (  400e6,  800e6)
 
     def __init__(self):
         self.reset      = Signal()