From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Sep 2022 17:31:35 +0000 (+0100)
Subject: sort out CR RM Mode (sz/dz bits moved, consistent)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a8f7300cf6ee58496219df61452cff13a9da88e;p=openpower-isa.git

sort out CR RM Mode (sz/dz bits moved, consistent)
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 1dc99c4c..8a129fd0 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1659,9 +1659,9 @@ class CROpBaseRM(BaseRM):
 
 class CROpSimpleRM(CROpBaseRM):
     """cr_op: simple mode"""
-    sz: BaseRM[6]
     SNZ: BaseRM[7]
     RG: BaseRM[20]
+    sz: BaseRM[21]
     dz: BaseRM[22]
 
     def specifiers(self, record):
@@ -1677,9 +1677,10 @@ class CROpSimpleRM(CROpBaseRM):
 
 class CROpScalarReduceRM(CROpBaseRM):
     """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
-    sz: BaseRM[6]
     SNZ: BaseRM[7]
     RG: BaseRM[20]
+    sz: BaseRM[21]
+    dz: BaseRM[22]
 
     def specifiers(self, record):
         if self.sz:
@@ -1695,8 +1696,8 @@ class CROpReservedRM(CROpBaseRM):
     zz: BaseRM[6]
     SNZ: BaseRM[7]
     RG: BaseRM[20]
-    dz: BaseRM[6]
     sz: BaseRM[6]
+    dz: BaseRM[6]
 
     def specifiers(self, record):
         if self.zz:
@@ -1709,13 +1710,12 @@ class CROpReservedRM(CROpBaseRM):
 
 class CROpFailFirst3RM(CROpBaseRM):
     """cr_op: ffirst 3-bit mode"""
-    zz: BaseRM[6]
     SNZ: BaseRM[7]
     VLI: BaseRM[20]
     inv: BaseRM[21]
     CR: BaseRM[22, 23]
-    dz: BaseRM[6]
-    sz: BaseRM[6]
+    sz: BaseRM[21]
+    dz: BaseRM[22]
 
     def specifiers(self, record):
         if self.zz: