From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 18:22:53 +0000 (-0700)
Subject: Add CHANGELOG entry
X-Git-Tag: working-ls180~1085^2~61
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a9031c48ed91de674f4ad1507b1148153930d0d;p=yosys.git

Add CHANGELOG entry
---

diff --git a/CHANGELOG b/CHANGELOG
index ca42df71e..92456df99 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "opt_share" pass, run as part of "opt -full"
     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
     - Removed "ice40_unlut"
+    - Added "xilinx_srl" for Xilinx shift register extraction
+    - Removed "shregmap -tech xilinx"
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------